22-Elec-B5 Advanced Electronics · December 2018

Question 1 of 5: Design of a CMOS Differential Amplifier

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, December 2018 — 16-Elec-B5 Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are ideal and supplies are ±15 V unless a question says otherwise; in schematics ground and chassis are common.

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3) — Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation). P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of feedback amplifiers).

Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain reading of the accompanying prose. In Question 1 the input pair M₁/M₂ is a p-channel pair whose common source node is fed by M₅, with M₃/M₄ as n-channel current-source loads — M₆ and M₇ are the two diode-connected devices of the reference string, not signal-path loads. In Question 4 the input v_IN drives the source of M₁ and the gate is tied to the R₁/R₂ tap, so the forward path is a common-gate stage; were the input on the gate, part (a)'s R_IN would be infinite and its 8 marks unearnable. Both readings are stated where they are used.

Question 1: Design of a CMOS Differential Amplifier (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single-stage CMOS differential amplifier on ±1.5 V rails, biased from one reference string, with every threshold magnitude equal and the two mobility-oxide products in a fixed ratio.

Design data, Question 1
Quantity	Symbol	Value
Supply rails	$V_{DD} = \|V_{SS}\|$	1.5 V
Threshold magnitude	$\|V_{TH}\|$	0.5 V
n-channel process constant	$\mu_n C_{ox}$	250 µA/V²
p-channel process constant	$\mu_p C_{ox}$	100 µA/V²
Channel-length modulation	$\lambda$	0.1 V⁻¹
Required differential gain	$A_d$	50 V/V
Reference and bias currents	$I_{ref} = I_{bias}$	200 µA
PMOS mirror gate voltage	$V_{G5} = V_{G6}$	+0.8 V
NMOS mirror gate voltage	$V_{G3} = V_{G4} = V_{G7}$	−0.8 V

Find. The reference resistor $R$, and for each of M₁ to M₇ the drain current $|I_{DS}|$, the gate-source voltage $|V_{GS}|$ and the aspect ratio $W/L$ that together meet all four specifications.

[Figure not reproduced: Figure 1.1 — The amplifier as printed, redrawn with the branch currents this design establishes. M 6 , R and M 7 form the reference string; M 5 mirrors it as the tail; M 1 /M 2 are the PMOS input pair and M 3 /M 4 are the NMOS current-source loads. See the official exam paper.]

Approach. Read the bias string first — it fixes every overdrive except that of the input pair — then take the pair's overdrive from the gain specification, and finally invert the saturation square law once per device.

Identify what each device does. M₆ (diode-connected PMOS), $R$ and M₇ (diode-connected NMOS) form a series string from $+V_{DD}$ to $-V_{SS}$ carrying $I_{ref}$. M₅ takes its gate from M₆ and therefore mirrors $I_{ref}$ into the amplifier as the tail current $I_{bias}$; M₃ and M₄ take their gates from M₇ and act as current-source loads. M₁ and M₂ are the p-channel input pair: their sources meet at the tail node, their drains are sunk by M₃ and M₄, and the output $v_{do}$ is taken differentially between the two drains. Nothing in the signal path is diode-connected, so both drain nodes are high impedance.
Convert the specified gate voltages into overdrives. For the p-channel mirror devices the source sits on $+V_{DD}$, so $$\begin{aligned}|V_{GS5}| &= |V_{GS6}| = V_{DD} - V_{G5} = 1.5 - 0.8 = 0.7\ \text{V} \\ |V_{ov5}| &= |V_{GS5}| - |V_{TH}| = 0.2\ \text{V}.\end{aligned}$$ For the n-channel mirror devices the source sits on $-V_{SS}$, so $V_{GS3} = V_{G3} - (-V_{SS}) = -0.8 + 1.5 = 0.7$ V and $V_{ov3} = 0.2$ V as well. The paper has chosen the two gate voltages so that every bias device runs at the same 0.2 V overdrive.
Assign the branch currents. The reference string carries $I_{ref} = 200\ \mu\text{A}$ through both M₆ and M₇. M₅ mirrors it, so the tail current is $I_{bias} = 200\ \mu\text{A}$; a balanced pair splits that equally, and each load must sink exactly what its half of the pair delivers: $$\boxed{\begin{aligned}|I_{D1}| &= |I_{D2}| = I_{D3} = I_{D4} = 100\ \mu\text{A} \\ |I_{D5}| &= |I_{D6}| = I_{D7} = 200\ \mu\text{A}\end{aligned}}$$
Size the reference resistor from the two diode drops. A diode-connected device holds its drain at its own gate voltage, so the top of $R$ sits at $V_{D6} = V_{G6} = +0.8$ V and the bottom at $V_{D7} = V_{G7} = -0.8$ V. The whole 1.6 V appears across $R$ at $I_{ref}$: $$R = \frac{V_{G6} - V_{G7}}{I_{ref}} = \frac{0.8 - (-0.8)}{200 \times 10^{-6}} = \boxed{8.0\ \text{k}\Omega}$$ This single resistor is what sets the whole bias point of the amplifier.
Find the output resistance the gain must work against. Channel-length modulation is neglected for the d.c. bias but is exactly what gives the loads their finite output resistance. With $\lambda = 0.1\ \text{V}^{-1}$ at 100 µA, $$\begin{aligned}r_{o2} &= r_{o4} = \frac{1}{\lambda I_D} = \frac{1}{0.1 \times 100 \times 10^{-6}} = 100\ \text{k}\Omega \\ r_{o2}\,\|\,r_{o4} &= 50\ \text{k}\Omega.\end{aligned}$$
Turn the gain specification into a transconductance. For a differential output taken between the two drains the differential half-circuit gives $A_d = g_{m1}(r_{o2}\,\|\,r_{o4})$, so $$g_{m1} = \frac{A_d}{r_{o2}\,\|\,r_{o4}} = \frac{50}{50 \times 10^{3}} = \boxed{1.0\ \text{mA/V}}$$
Recover the input pair's overdrive and gate drive. Using $g_m = 2 I_D / |V_{ov}|$ at the 100 µA found in step 3, $$\begin{aligned}|V_{ov1}| &= \frac{2 I_{D1}}{g_{m1}} = \frac{2(100 \times 10^{-6})}{1.0 \times 10^{-3}} = 0.20\ \text{V} \\ |V_{GS1}| &= |V_{TH}| + |V_{ov1}| = 0.70\ \text{V}.\end{aligned}$$ The input pair therefore also lands at a 0.2 V overdrive — a pleasant consequence of the numbers chosen, not something imposed.
Invert the square law once per device. In saturation $I_D = \tfrac{1}{2}\mu C_{ox}(W/L)V_{ov}^{2}$, hence $W/L = 2 I_D / (\mu C_{ox} V_{ov}^{2})$ with $\mu_p C_{ox} = \mu_n C_{ox}/2.5 = 100\ \mu\text{A/V}^2$. Every overdrive is 0.2 V, so $V_{ov}^2 = 0.04\ \text{V}^2$ throughout and the ratios follow directly: $$\begin{aligned}\left(\frac{W}{L}\right)_{1,2} &= \frac{2(100\,\mu)}{(100\,\mu)(0.04)} = 50 \\ \left(\frac{W}{L}\right)_{3,4} &= \frac{2(100\,\mu)}{(250\,\mu)(0.04)} = 20\end{aligned}$$ $$\begin{aligned}\left(\frac{W}{L}\right)_{5,6} &= \frac{2(200\,\mu)}{(100\,\mu)(0.04)} = 100 \\ \left(\frac{W}{L}\right)_{7} &= \frac{2(200\,\mu)}{(250\,\mu)(0.04)} = 40.\end{aligned}$$ The mirror ratios fall out as they must: M₅:M₆ is 1:1 because $I_{bias} = I_{ref}$, while M₃:M₇ and M₄:M₇ are 1:2 because each load carries half the tail.
Confirm the operating point is legal. With the input gates at 0 V d.c. the pair's common source node sits at $|V_{GS1}| = +0.70$ V, leaving M₅ with $|V_{DS5}| = 1.5 - 0.7 = 0.8\ \text{V} \gg 0.2$ V of headroom. The output d.c. level may sit anywhere between $-V_{SS} + V_{ov3} = -1.30$ V (below which the loads leave saturation) and $V_{S1} - |V_{ov1}| = +0.50$ V (above which the pair does), a comfortable 1.8 V window on a 3 V total supply.

Every specification is now met simultaneously, and the design is described completely by one resistor and seven aspect ratios.

Final results, Question 1
Device	Type	Role	$\|I_{DS}\|$	$\|V_{GS}\|$	$\|V_{ov}\|$	$W/L$
M₁	PMOS	input pair	100 µA	0.70 V	0.20 V	50
M₂	PMOS	input pair	100 µA	0.70 V	0.20 V	50
M₃	NMOS	current-source load	100 µA	0.70 V	0.20 V	20
M₄	NMOS	current-source load	100 µA	0.70 V	0.20 V	20
M₅	PMOS	tail current source	200 µA	0.70 V	0.20 V	100
M₆	PMOS	mirror reference (diode)	200 µA	0.70 V	0.20 V	100
M₇	NMOS	mirror reference (diode)	200 µA	0.70 V	0.20 V	40
$R$	—	sets $I_{ref}$	8.0 kΩ
$g_{m1}$	—	pair transconductance	1.0 mA/V
$A_d$	—	achieved differential gain	50 V/V

Check: the gain is set by the overdrive alone. Substituting $g_m = 2I_D/|V_{ov}|$ and $r_o = 1/(\lambda I_D)$ into $A_d = g_m(r_o\,\|\,r_o)$ collapses every current out of the expression and leaves $A_d = V_A/|V_{ov}| = 10/0.2 = 50$, with $V_A = 1/\lambda = 10$ V. The design is therefore independent of the bias current: had the paper asked for the same gain at 400 µA the aspect ratios would double and the gain would not move. Note also that the problem asks for channel-length modulation to be ignored for the d.c. calculations while retaining $\lambda$ in $r_o$ — the two uses are not in conflict, and dropping $\lambda$ from $r_o$ as well would make the gain infinite.

Topic. Biasing and gain of a single-stage CMOS differential amplifier with current-source loads, referenced from a resistor-programmed mirror string.

Key relations. Saturation current $I_D = \tfrac{1}{2}\mu C_{ox}(W/L)V_{ov}^2$; transconductance $g_m = 2I_D/V_{ov} = \sqrt{2\mu C_{ox}(W/L)I_D}$; output resistance $r_o = 1/(\lambda I_D) = V_A/I_D$; differential gain with a differential output $A_d = g_m(r_{oN}\,\|\,r_{oP})$; intrinsic gain $g_m r_o = 2V_A/V_{ov}$.

Why this works. A current mirror forces a known current by forcing a known gate-source voltage, and a diode-connected device is simply the mirror's way of manufacturing that voltage from a current. Once the string current is fixed by $R$, every mirrored branch is set by an aspect-ratio ratio rather than by an absolute process parameter, which is why integrated bias circuits are built this way. On the signal side the two drains are loaded only by output resistances, so the gain is the transconductance times a parallel pair of $r_o$ values, and because both the pair and the loads carry the same current, that gain reduces to a pure ratio of Early voltage to overdrive.

Common pitfall. Two errors dominate. The first is reading M₆ as an active mirror load on M₂, which halves or doubles the answer depending on which way the mistake runs; here M₆ sits in the reference string and the output is differential, so no current recombination occurs. The second is forgetting that the pair splits the tail, and sizing M₁/M₂ for 200 µA instead of 100 µA — which doubles both aspect ratios and halves the gain.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §8.2 (the MOS differential pair) and §8.5 (differential amplifiers with active loads); Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., §4.3 and §5.1 (current mirrors and biasing).

← Paper overview Next: Question 2 →