22-Elec-B5 Advanced Electronics · December 2018

Question 4 of 5: Input and Output Resistance of a Feedback Amplifier

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, December 2018 — 16-Elec-B5 Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are ideal and supplies are ±15 V unless a question says otherwise; in schematics ground and chassis are common.

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3) — Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation). P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of feedback amplifiers).

Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain reading of the accompanying prose. In Question 1 the input pair M₁/M₂ is a p-channel pair whose common source node is fed by M₅, with M₃/M₄ as n-channel current-source loads — M₆ and M₇ are the two diode-connected devices of the reference string, not signal-path loads. In Question 4 the input v_IN drives the source of M₁ and the gate is tied to the R₁/R₂ tap, so the forward path is a common-gate stage; were the input on the gate, part (a)'s R_IN would be infinite and its 8 marks unearnable. Both readings are stated where they are used.

Question 4: Input and Output Resistance of a Feedback Amplifier (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single saturated MOSFET with drain resistor $R_D$ to $+V_{DD}$ and an ideal current source $I_{BIAS}$ in the source lead to $-V_{DD}$. The input $v_{IN}$ is applied at the source, the output $v_{OUT}$ is taken at the drain, and the divider $R_1$ (drain to gate) with $R_2$ (gate to ground) returns a fraction of the output to the gate. The answer is to be expressed in $g_m$, $R_D$, $R_1$ and $R_2$ only, so $r_o$ is taken as infinite and the ideal $I_{BIAS}$ contributes no conductance at the source.

Find. $R_{IN}$ looking into the source and $R_{OUT}$ looking into the drain, first with the feedback network removed and then with $R_1$ and $R_2$ finite.

[Figure not reproduced: Figure 4.1 — The feedback amplifier as printed. The input drives the source of M 1 , the gate is tied to the R 1 /R 2 tap, and R OUT is measured at the drain. See the official exam paper.]

Approach. Identify the forward path and the feedback topology from the terminal assignments, then obtain each resistance from a direct small-signal node analysis, using the feedback formalism only to interpret the result.

Part (a) — collapse the network and name the stage. Setting $R_1 \to \infty$ and $R_2 \to 0$ ties the gate straight to ground. With the input on the source and the output on the drain, what remains is a plain common-gate stage. This is the reading the printed figure supports; had $v_{IN}$ been on the gate, the input resistance would be infinite and the eight marks of part (a) would have nothing to measure.
Get the open-loop input resistance. Inject a test current $i$ into the source. The gate is grounded, so $v_{gs} = -v_s$ and the device's drain current is $g_m v_{gs} = -g_m v_s$; that current must leave the source node and balance the injected current, giving $i = g_m v_s$ and $$R_{IN} = \frac{v_s}{i} = \boxed{\frac{1}{g_m}}$$ Looking into a source is always a low-resistance proposition — this is the property that makes the common-gate stage a current buffer.
Get the open-loop output resistance. To measure at the drain, set $v_{IN} = 0$, which grounds the source. With gate and source both grounded $v_{gs} = 0$, the controlled source is dead, and (with $r_o$ neglected as instructed) the drain sees only the load resistor: $$R_{OUT} = \boxed{R_D}$$
Part (b) — classify the feedback. The divider samples the output voltage at the drain and returns a voltage to the gate, where it is compared with $v_{IN}$ at the source through the device's own $v_{gs}$: the comparison is a subtraction of voltages in series. This is series-shunt (voltage-series) feedback, with feedback factor $$\beta = \frac{R_2}{R_1+R_2}.$$ Series mixing should raise the input resistance and shunt sampling should lower the output resistance, and both predictions are borne out below.
Write the three node equations. With a test current $i$ into the source, and $v_g$, $v_s$, $v_d$ the small-signal node voltages, the gate draws no current, the source node balances the injected current against the device current, and the drain node balances the device current against $R_D$ and $R_1$: $$\begin{aligned}\frac{v_g-v_d}{R_1}+\frac{v_g}{R_2} &=0 \\ i + g_m(v_g-v_s) &= 0 \\ g_m(v_g-v_s) + \frac{v_d}{R_D} + \frac{v_d-v_g}{R_1} &= 0 .\end{aligned}$$ The first equation gives $v_g = \beta v_d$ immediately.
Solve for the closed-loop input resistance. The source equation gives $v_s = v_g + i/g_m$, and substituting $v_g = \beta v_d$ into the drain equation collapses the two divider terms into one: $$v_d\left[\frac{1}{R_D}+\frac{1}{R_1+R_2}\right] = i \;\Longrightarrow\; v_d = \frac{i\,R_D(R_1+R_2)}{R_D+R_1+R_2}.$$ Hence $v_g = \beta v_d = i R_D R_2/(R_D+R_1+R_2)$ and $$R_{IN} = \frac{v_s}{i} = \boxed{\frac{1}{g_m} + \frac{R_D R_2}{R_D + R_1 + R_2}}$$ The feedback has added a positive term to $1/g_m$, exactly as series mixing requires.
Solve for the closed-loop output resistance. Zero $v_{IN}$ so the source is grounded, drive the drain with $v_d$, and sum the currents it must supply: into $R_D$, into the divider chain, and into the device, whose drain current is now $g_m v_g = g_m\beta v_d$ because the gate is no longer at ground: $$i = v_d\left[\frac{1}{R_D}+\frac{1}{R_1+R_2}+\frac{g_m R_2}{R_1+R_2}\right],$$ $$R_{OUT} = \boxed{R_D \,\|\, (R_1+R_2) \,\|\, \frac{R_1+R_2}{g_m R_2}}$$ The third term is the feedback's own contribution; without it the expression is just the passive loading of the divider.
Check the limits and the direction of each change. Letting $R_1\to\infty$ with $R_2\to 0$ sends the added term in $R_{IN}$ to zero and both divider terms in $R_{OUT}$ to zero, recovering $1/g_m$ and $R_D$ from part (a) exactly. For any finite network $R_{IN} > 1/g_m$ and $R_{OUT} < R_D$, which is the signature of this topology.
Put numbers on it to show the size of the effect. Taking $g_m = 5$ mA/V, $R_D = 4$ kΩ, $R_1 = 36$ kΩ and $R_2 = 4$ kΩ gives $\beta = 0.1$ and a loop gain $g_m R_D \beta = 2.0$: $R_{IN}$ rises from 200 Ω to 564 Ω, and $R_{OUT}$ falls from 4.00 kΩ to 1.29 kΩ.

Final results, Question 4
Part	Quantity	Closed form	Illustrative value
(a)	$R_{IN}$	$1/g_m$	200 Ω
(a)	$R_{OUT}$	$R_D$	4.00 kΩ
(b)	$R_{IN}$	$\dfrac{1}{g_m}+\dfrac{R_D R_2}{R_D+R_1+R_2}$	564 Ω
(b)	$R_{OUT}$	$R_D\,\\|\,(R_1+R_2)\,\\|\,\dfrac{R_1+R_2}{g_mR_2}$	1.29 kΩ
(b)	Feedback factor	$\beta = R_2/(R_1+R_2)$	0.100
(b)	Loop gain	$g_m R_D \beta$	2.00

Check: two modelling assumptions are forced by the question's own wording. Because the answer must contain only $g_m$, $R_D$, $R_1$ and $R_2$, the device output resistance $r_o$ is taken as infinite and the source current source $I_{BIAS}$ as ideal. Retaining a finite $r_o$ would add a $r_o + R_D$ path from source to drain and would reduce $R_{OUT}$ slightly; the topology and the direction of every feedback effect are unchanged. The terminal assignment — input on the source, gate on the divider tap — was confirmed on the printed schematic and is what makes part (a) answerable.

Topic. Series-shunt (voltage-series) feedback around a common-gate forward path, and its effect on the two terminal resistances.

Key relations. Common-gate open loop: $R_{IN}=1/g_m$, $R_{OUT}=R_D$. Feedback factor $\beta = R_2/(R_1+R_2)$. Closed loop: $R_{IN}=1/g_m + R_DR_2/(R_D+R_1+R_2)$ and $R_{OUT}=[1/R_D + 1/(R_1+R_2) + g_m\beta]^{-1}$. Limits: $R_1\to\infty$, $R_2\to 0$ must reproduce the open-loop pair.

Why this works. Feedback changes a terminal resistance in the direction that makes the amplifier behave more like the quantity it is trying to hold. Sampling the output voltage makes the output look more like a voltage source, so $R_{OUT}$ falls; mixing in series at the input makes the input look more like a voltage input, so $R_{IN}$ rises. The useful discipline here is not to trust the textbook $(1+A\beta)$ factors blindly, because they assume an idealised, unloaded feedback network. Working the three node equations directly costs six lines, gives exact expressions, and automatically includes the loading of $R_1$ and $R_2$ on both ports — loading that is responsible for most of the numerical answer.

Common pitfall. Reading the input as being on the gate. That makes $R_{IN}$ infinite, renders part (a) meaningless, and turns the circuit into a shunt-shunt topology with entirely different formulas. The second pitfall is quoting $R_{OUT} = R_D/(1+g_mR_D\beta)$ from the idealised feedback result, which drops the $R_1+R_2$ shunt path and is wrong by about 30 percent for the values used above.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §12.4 (the series-shunt feedback amplifier) and §12.7 (determining the loop gain); Gray, Hurst, Lewis & Meyer, 5th ed., Ch. 8 (feedback).

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