Question 3 of 5: Miller Compensation of a Two-Pole Op Amp
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2018 — 16-Elec-B5
Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp
calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are
ideal and supplies are ±15 V unless a question says otherwise; in schematics
ground and chassis are common.
Reference texts. A. S. Sedra and K. C. Smith,
Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3)
— Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power
amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned
amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed.,
Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation).
P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of
feedback amplifiers).
Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain
reading of the accompanying prose. In Question 1 the input pair M1/M2
is a p-channel pair whose common source node is fed by M5, with
M3/M4 as n-channel current-source loads — M6
and M7 are the two diode-connected devices of the reference string, not
signal-path loads. In Question 4 the input vIN drives the source of
M1 and the gate is tied to the R1/R2 tap, so the
forward path is a common-gate stage; were the input on the gate, part (a)'s RIN
would be infinite and its 8 marks unearnable. Both readings are stated where they are
used.
Question 3: Miller Compensation of a Two-Pole Op Amp (20 marks)
Given. A two-node model of a transconductance stage: an input node of
resistance $R_1$ shunted by $C_1$, an output node of resistance $R_L$ shunted by $C_L$,
and a compensation capacitor $C_C$ bridging the two. The two open-loop pole frequencies
and the 100 dB d.c. gain read off the supplied Bode plot fix the two node resistances.
Given data, Question 3
Quantity
Symbol
Value
Input node capacitance
$C_1$
100 pF
Output node capacitance
$C_L$
5 pF
Transconductance
$g_m$
40 mA/V
Open-loop first pole
$f_{P1}$
0.1 MHz
Open-loop second pole
$f_{P2}$
1 MHz
Open-loop d.c. gain (from the plot)
$A_0$
100 dB
Find. A value of $C_C$ that makes the amplifier stable in unity-gain
feedback, the reasoning behind it, the two new pole frequencies, and the resulting phase
margin.
Figure 3.1 — The supplied equivalent circuit, annotated with the node resistances recovered from the two printed pole frequencies. CC bridges the input and output nodes.
Approach. Recover the node resistances from the printed poles, write
the exact two-pole denominator with $C_C$ present, choose $C_C$ from an explicit
stability criterion rather than from the dominant pole alone, and then read the new poles
and the phase margin off that same denominator.
Recover the node resistances. Each uncompensated pole is the
$RC$ product of its own node, so
$$\begin{aligned}R_1 &= \frac{1}{2\pi f_{P1} C_1} = \frac{1}{2\pi (10^5)(100\ \text{pF})}
= 15.92\ \text{k}\Omega \\ R_L &= \frac{1}{2\pi f_{P2} C_L} = \frac{1}{2\pi (10^6)(5\ \text{pF})}
= 31.83\ \text{k}\Omega.\end{aligned}$$
The output stage alone therefore contributes $g_m R_L = 1273$, or 62.1 dB, of the 100 dB
total — a reminder that $A_0$ must be read from the plot and not computed from
$g_m R_L$.
Show why compensation is needed at all. With
$A_0 = 10^{100/20} = 10^5$ and both poles far below crossover, the loop crosses unity on
the −40 dB/decade segment at
$$f_{t,\text{unc}} = \sqrt{A_0 f_{P1} f_{P2}} = \sqrt{(10^5)(10^5)(10^6)} = 100\ \text{MHz},$$
where the phase lag is
$180^\circ - \arctan(f_t/f_{P1}) - \arctan(f_t/f_{P2}) = 0.6^\circ$ of margin. In unity-gain
feedback the amplifier is on the edge of oscillation, which is exactly what the supplied
plot shows for the low-$1/\beta$ (50 dB) case.
Write the exact denominator with $C_C$ in place. Two node equations
with the bridging capacitor give $V_o/I_s$ a denominator
$D(s) = 1 + b_1 s + b_2 s^2$ with
$$\begin{aligned}b_1 &= C_1R_1 + C_LR_L + C_C\left(g_m R_1 R_L + R_1 + R_L\right) \\ b_2 &= R_1R_L\left[C_1C_L + C_C(C_1+C_L)\right].\end{aligned}$$
Because the roots are real and widely separated, the new poles are
$f'_{P1} = 1/(2\pi b_1)$ and $f'_{P2} = b_1/(2\pi b_2)$. The term $g_m R_1 R_L C_C$
dominates $b_1$: that is Miller multiplication pulling the first pole down, while $b_2$
grows only linearly in $C_C$, which is what pushes the second pole up. The pair
of movements is what "pole splitting" means.
State the stability criterion before choosing a value. This is a
design question with one free parameter, so the criterion must be declared. Placing the
unity-gain crossover at half the second pole,
$$f_t = A_0 f'_{P1} = \tfrac{1}{2} f'_{P2},$$
buys a phase margin near 63° — a well-damped, non-peaking closed-loop response.
(Setting $f_t = f'_{P2}$ instead would leave only 45° and a visibly peaked step
response.) Substituting the two expressions above reduces the criterion to the single
equation $b_1^{\,2} = 2A_0 b_2$, one quadratic in $C_C$, whose positive root is
29.7 pF.
Choose a standard value and evaluate the new poles. Rounding up to
the nearest convenient value, take
$$\boxed{C_C = 30\ \text{pF}}$$
which puts $b_1 = 611\ \mu\text{s}$ and $b_2 = 1.85 \times 10^{-12}\ \text{s}^2$, so
$$\boxed{\begin{aligned}f'_{P1} &= 260\ \text{Hz} \\ f'_{P2} &= 52.6\ \text{MHz}\end{aligned}}$$
The first pole has moved down by a factor of 384 and the second up by a factor of 53 from
their uncompensated positions.
Find the crossover and the phase margin. With a single dominant pole
the gain falls at 20 dB/decade to
$f_t = A_0 f'_{P1} = 10^5 \times 260 = 26.0$ MHz, and
$$\text{PM} = 180^\circ - \arctan\!\frac{f_t}{f'_{P1}} - \arctan\!\frac{f_t}{f'_{P2}}
= 180^\circ - 90.0^\circ - 26.3^\circ = \boxed{63.7^\circ}$$
Comfortably stable, and by construction: the second pole sits one octave above
crossover, so it can only remove about 26°.
Charge the right-half-plane zero. The feed-forward path through
$C_C$ puts a zero at
$f_z = g_m/(2\pi C_C) = 212$ MHz. It adds gain but subtracts phase, so the
honest margin is
$$\text{PM}_z = 63.7^\circ - \arctan\!\frac{f_t}{f_z}
= 63.7^\circ - 7.0^\circ = 56.7^\circ,$$
still well damped. The zero sits eight times above crossover here only because $g_m$ is
large; in a low-power design it would be the limiting factor and would need a nulling
resistor in series with $C_C$.
Check the result against the physical ceiling, and against the naive
design. No amount of $C_C$ can push the second pole past
$g_m/[2\pi(C_1+C_L)] = 60.6$ MHz, and 52.6 MHz respects that. More instructively, a
designer who assumes the second pole stays at 1 MHz and lowers the crossover to
0.5 MHz by Miller multiplication alone would specify
$$C_C = \frac{1}{2\pi f'_{P1}R_1(1+g_mR_L)} - \frac{C_1}{1+g_mR_L} \approx 1570\ \text{pF},$$
52 times larger, for a closed-loop bandwidth of 0.5 MHz instead of 26 MHz. Recognising
that the second pole moves is the whole point of the technique.
Figure 3.2 — Open-loop magnitude asymptotes before and after compensation. The 30 pF capacitor drags the first pole from 0.1 MHz to 260 Hz and pushes the second from 1 MHz to 52.6 MHz.