Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2018 — 16-Elec-B5
Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp
calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are
ideal and supplies are ±15 V unless a question says otherwise; in schematics
ground and chassis are common.
Reference texts. A. S. Sedra and K. C. Smith,
Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3)
— Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power
amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned
amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed.,
Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation).
P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of
feedback amplifiers).
Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain
reading of the accompanying prose. In Question 1 the input pair M1/M2
is a p-channel pair whose common source node is fed by M5, with
M3/M4 as n-channel current-source loads — M6
and M7 are the two diode-connected devices of the reference string, not
signal-path loads. In Question 4 the input vIN drives the source of
M1 and the gate is tied to the R1/R2 tap, so the
forward path is a common-gate stage; were the input on the gate, part (a)'s RIN
would be infinite and its 8 marks unearnable. Both readings are stated where they are
used.
Given. A complementary emitter-follower output stage driven by a
sinusoid, with each device conducting for one half cycle only and base currents
negligible, so the collector and emitter currents of the conducting device are equal to
the load current.
Given data, Question 2
Quantity
Symbol
Value
Positive and negative rails
$V_{CC} = |V_{EE}|$
10 V
Load resistance
$R_L$
8 Ω
Conduction angle per device
—
180° (class B)
Base current
$i_B$
negligible
Bias-source power
$I_1,\ I_2$
neglected
Find. The maximum average power delivered to $R_L$, the average power
then dissipated in $Q_1$, and the corresponding maximum conversion efficiency.
Figure 2.1 — Complementary push-pull output stage. Q1 carries the positive half cycle into RL, Q2 the negative half; D1, D2, I1 and I2 pre-bias the bases and take no part in the power calculation.
Approach. Fix the largest undistorted output swing from the rails,
then integrate the instantaneous device power over the half cycle in which that device
conducts, and finally divide load power by supply power.
Part (a) — establish the maximum swing. Each device is an
emitter follower whose collector sits on its own rail, so the output can rise to within
one saturation voltage of $+V_{CC}$ and fall to within one of $-V_{EE}$. The paper gives
no $V_{CE(\text{sat})}$, so with an ideal drive the peak output is the rail itself:
$$\begin{aligned}\hat{V}_o &= V_{CC} = 10\ \text{V} \\ \hat{I}_o &= \frac{\hat{V}_o}{R_L} = \frac{10}{8} = 1.25\ \text{A}.\end{aligned}$$
In rms terms this is $V_{o,\text{rms}} = 10/\sqrt{2} = 7.071$ V across
$I_{o,\text{rms}} = 0.884$ A.
Compute the load power. For a sinusoid the average power is the
product of the rms quantities, which is the familiar half-square:
$$P_L = \frac{\hat{V}_o^{\,2}}{2 R_L} = \frac{(10)^2}{2(8)} = \boxed{6.25\ \text{W}}$$
This is the maximum average (the question's "rms") power the stage can deliver
into 8 Ω from ±10 V rails.
Part (b) — set up the dissipation integral for one device.
$Q_1$ conducts only while the output is positive. During that half cycle it stands off
$v_{CE1} = V_{CC} - \hat{V}_o \sin\theta$ while passing
$i_{C1} = (\hat{V}_o/R_L)\sin\theta$; during the other half cycle it is off and
dissipates nothing. Averaging over the full period,
$$P_{D1} = \frac{1}{2\pi}\int_{0}^{\pi}
\left(V_{CC} - \hat{V}_o \sin\theta\right)\frac{\hat{V}_o}{R_L}\sin\theta\; d\theta .$$
Evaluate it. Using
$\int_0^{\pi}\sin\theta\,d\theta = 2$ and
$\int_0^{\pi}\sin^2\theta\,d\theta = \pi/2$, the integral separates into a supply term
and a load term:
$$P_{D1} = \frac{V_{CC}\hat{V}_o}{\pi R_L} - \frac{\hat{V}_o^{\,2}}{4R_L}
= \frac{(10)(10)}{\pi(8)} - \frac{(10)^2}{4(8)} = 3.979 - 3.125
= \boxed{0.854\ \text{W}}$$
Note the second term is exactly half the load power, as it must be: the two devices
between them supply all of it.
Part (c) — get the supply power. Each rail delivers a
half-sine of average value $\hat{I}_o/\pi$, so together
$$P_S = 2 V_{CC}\,\frac{\hat{V}_o}{\pi R_L} = \frac{2(10)(10)}{\pi (8)} = 7.958\ \text{W}.$$
Divide to get the efficiency.
$$\eta = \frac{P_L}{P_S}
= \frac{\hat{V}_o^{\,2}/(2R_L)}{2V_{CC}\hat{V}_o/(\pi R_L)}
= \frac{\pi}{4}\cdot\frac{\hat{V}_o}{V_{CC}}
= \frac{\pi}{4} = \boxed{78.5\ \%}$$
at full swing, which is the textbook class-B ceiling and roughly three times what a
class-A follower of the same rails would manage.
Check the power balance. Everything drawn from the rails must
appear either in the load or in the two devices:
$$P_S - P_L = 7.958 - 6.250 = 1.708\ \text{W} = 2 P_{D1} = 2(0.854)\ \text{W}. \checkmark$$
This one-line check catches an arithmetic slip in any of the three parts.
Note where the thermal design point actually is. Device dissipation
is not greatest at full output. Differentiating $P_{D1}$ with respect to
$\hat{V}_o$ gives a maximum at
$\hat{V}_o = 2V_{CC}/\pi = 6.37$ V, where
$$P_{D1(\text{max})} = \frac{V_{CC}^{\,2}}{\pi^2 R_L} = \frac{100}{\pi^2 (8)}
= 1.267\ \text{W},$$
half again the 0.854 W computed in part (b). A heat sink sized on the part (b) number
alone would be undersized by 48 percent.
Final results, Question 2
Part
Quantity
Value
(a)
Peak output voltage / current
10.0 V / 1.25 A
(a)
Maximum average power in $R_L$
6.25 W
(b)
Average dissipation in $Q_1$ at full output
0.854 W
(c)
Total supply power at full output
7.96 W
(c)
Maximum power efficiency
78.5 % ($\pi/4$)
—
Worst-case dissipation per device
1.267 W at $\hat{V}_o = 6.37$ V
Figure 2.2 — Load power and per-device dissipation against peak output swing. Load power grows as the square of the swing while dissipation peaks at 1.267 W near 6.37 V, well before full output.
Check: the answers assume an ideal drive and zero
saturation voltage. The question supplies neither $V_{CE(\text{sat})}$ nor the
diode drops, so the peak output has been taken as the full rail. If a representative
$V_{CE(\text{sat})} = 0.3$ V is charged to each device the peak falls to 9.7 V and the
three answers become $P_L = 5.88$ W, $P_{D1} = 0.919$ W and $\eta = 76.2\ \%$ —
a five percent change that does not alter the method or the conclusion. Note also that
"rms power" in parts (a) and (b) is loose wording for average power; power has no rms
value, and it is the voltage and current that are rms.
