Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, December 2018 — 16-Elec-B5
Advanced Electronics. Three hours; CLOSED BOOK, an approved Casio or Sharp
calculator permitted. Five questions, all to be answered, 20 marks each. Op-amps are
ideal and supplies are ±15 V unless a question says otherwise; in schematics
ground and chassis are common.
Reference texts. A. S. Sedra and K. C. Smith,
Microelectronic Circuits, 8th ed. (the paper cites it by name for Question 3)
— Ch. 8 differential and multistage amplifiers, Ch. 10 output stages and power
amplifiers, Ch. 11 frequency response and compensation, Ch. 12 feedback, Ch. 17 tuned
amplifiers. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed.,
Ch. 4 (differential amplifiers) and Ch. 10 (stability and frequency compensation).
P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Ch. 4 (current mirrors) and Ch. 9 (frequency response of
feedback amplifiers).
Check: figure readings taken from the printed schematics. Three of the five figures need careful reading, and two of them contradict a plain
reading of the accompanying prose. In Question 1 the input pair M1/M2
is a p-channel pair whose common source node is fed by M5, with
M3/M4 as n-channel current-source loads — M6
and M7 are the two diode-connected devices of the reference string, not
signal-path loads. In Question 4 the input vIN drives the source of
M1 and the gate is tied to the R1/R2 tap, so the
forward path is a common-gate stage; were the input on the gate, part (a)'s RIN
would be infinite and its 8 marks unearnable. Both readings are stated where they are
used.
Question 5: Tuned Amplifier with a Gate Tank (20 marks)
Given. A common-source stage whose gate carries a parallel
$L_1\|C_1$ tank to ground, driven from $v_S$ through $R_S$, with a plain resistive drain
load $R_L$ and the source bypassed to ground by $C_2 = \infty$.
Given data, Question 5
Quantity
Symbol
Value
Transconductance parameter
$K$
1 mA/V2
Threshold voltage
$V_{TH}$
1 V
Gate-source capacitance
$C_{gs}$
10 pF
Gate-drain capacitance
$C_{gd}$
1 pF
Channel-length modulation
$\lambda$
0
Tank inductance / capacitance
$L_1$ / $C_1$
1 µH / 200 pF
Source bypass capacitor
$C_2$
∞ (a.c. short)
Source and load resistance
$R_S$ / $R_L$
1 kΩ / 2 kΩ
Bias current and supply
$I_{bias}$ / $V_{DD}$
2 mA / 10 V
Find. The centre frequency $\omega_o$, the voltage gain
$v_{OUT}/v_S$ at that frequency, and the 3 dB bandwidth.
Figure 5.1 — Tuned amplifier with the parallel L1||C1 tank at the gate. C2 places the source at a.c. ground; the drain carries only the resistive load RL.
Approach. Bias the device to get $g_m$, add every capacitance that
appears in parallel with the tank (including the Miller-multiplied $C_{gd}$), then read
the resonance, the resonant gain and the bandwidth off the resulting parallel $RLC$.
Part (a) — establish the operating point. Taking the paper's
transconductance parameter in the usual square-law form
$I_D = \tfrac{1}{2}K V_{ov}^{2}$ and differentiating, the standard result
$g_m = \sqrt{2KI_{bias}}$ applies:
$$\begin{aligned}g_m &= \sqrt{2(1\times10^{-3})(2\times10^{-3})} = 2.0\ \text{mA/V} \\ V_{ov} &= \sqrt{\frac{2I_{bias}}{K}} = 2.0\ \text{V}\end{aligned}$$
so $V_{GS} = V_{TH}+V_{ov} = 3.0$ V and the quiescent drain sits at
$V_{DD} - I_{bias}R_L = 10 - 4 = 6.0$ V. The inductor grounds the gate at d.c., so the
source rests at −3.0 V and $V_{DS} = 9.0\ \text{V} \gg V_{ov}$: firmly saturated.
Collect the total tank capacitance. $C_2$ shorts the source to
ground for signals, so $C_{gs}$ hangs directly across the tank. $C_{gd}$ bridges gate to
drain and is therefore Miller-multiplied by the stage gain:
$$C_{\text{Miller}} = C_{gd}\left(1+g_mR_L\right) = 1\left(1+4\right) = 5\ \text{pF},$$
$$C_{\text{tot}} = C_1 + C_{gs} + C_{gd}(1+g_mR_L) = 200 + 10 + 5 = \boxed{215\ \text{pF}}$$
This is why the question bothers to supply $C_{gs}$ and $C_{gd}$ at all.
Compute the centre frequency. The tank resonates where its
susceptance vanishes:
$$\omega_o = \frac{1}{\sqrt{L_1 C_{\text{tot}}}}
= \frac{1}{\sqrt{(1\times10^{-6})(215\times10^{-12})}}
= \boxed{6.82\times10^{7}\ \text{rad/s}\;\;(10.85\ \text{MHz})}$$
Ignoring the device capacitances would have given $7.07\times10^{7}$ rad/s, an error of
3.6 percent — small here, but it is precisely the error the question is testing
for.
Part (b) — see what the tank does to the drive. At resonance a
lossless parallel $L\|C$ is an open circuit, so no current flows through $R_S$, no voltage
is dropped across it, and the gate sees the full source:
$$v_{IN}(\omega_o) = v_S .$$
Away from resonance the tank loads $R_S$ and the gate voltage falls, which is what makes
the response band-pass.
Get the resonant gain. With $\lambda = 0$ the drain load is $R_L$
alone, so the common-source gain applies unmodified and, because the gate divider is
unity at $\omega_o$, it is also the overall gain:
$$\frac{v_{OUT}}{v_S}\bigg|_{\omega_o} = \frac{v_{OUT}}{v_{IN}}\cdot\frac{v_{IN}}{v_S}
= \left(-g_mR_L\right)(1) = -\left(2\times10^{-3}\right)\left(2\times10^{3}\right)
= \boxed{-4.0}$$
i.e. a magnitude of 4 with 180° of phase inversion.
Part (c) — identify what damps the tank. The only resistance
across the tank is the source resistance $R_S$; $R_L$ sits in the drain and cannot damp a
gate-side tank. For a parallel $RLC$ the 3 dB bandwidth is set by that shunt resistance
and the total capacitance alone:
$$\text{BW} = \frac{1}{R_S C_{\text{tot}}}
= \frac{1}{(1\times10^{3})(215\times10^{-12})}
= \boxed{4.65\times10^{6}\ \text{rad/s}\;\;(740\ \text{kHz})}$$
Cross-check through the quality factor. Two independent routes to
$Q$ must agree:
$$\begin{aligned}Q &= \frac{\omega_o}{\text{BW}} = \frac{6.82\times10^{7}}{4.65\times10^{6}} = 14.66 \\ Q &= R_S\sqrt{\frac{C_{\text{tot}}}{L_1}}
= 1000\sqrt{\frac{215\ \text{pF}}{1\ \mu\text{H}}} = 14.66. \checkmark\end{aligned}$$
Agreement to four figures confirms that $\omega_o$, BW and $C_{\text{tot}}$ are mutually
consistent.
Confirm against an exact solution. Solving the two-node network
without the Miller approximation — keeping $C_{gd}$ as a genuine feedback branch
— puts the peak at $6.820\times10^{7}$ rad/s with a magnitude of 3.79 and a 3 dB
bandwidth of $4.87\times10^{6}$ rad/s. The closed forms are therefore 5 percent
optimistic on gain and 4.6 percent low on bandwidth, because $Y_{gd}$ has a real part
that quietly shunts $R_S$. That is well inside examination tolerance, but it is the
reason the boxed answers should be quoted as the design values rather than as exact
ones.
Figure 5.2 — Exact two-node response magnitude, computed with Cgd retained as a feedback branch. The peak is 3.79 against the closed-form 4.0, and the exact bandwidth is 4.87 × 106 rad/s.
Final results, Question 5
Part
Quantity
Value
—
Transconductance $g_m$
2.0 mA/V
—
Overdrive / gate drive
2.0 V / 3.0 V
—
Total tank capacitance
215 pF
(a)
Centre frequency $\omega_o$
$6.82\times10^{7}$ rad/s (10.85 MHz)
(b)
Gain $v_{OUT}/v_S$ at $\omega_o$
−4.0 (exact solve: 3.79)
(c)
3 dB bandwidth
$4.65\times10^{6}$ rad/s (740 kHz)
—
Quality factor $Q$
14.66
Check: the bias source is understood to return to a
negative supply. The schematic draws $I_{bias}$ from the source terminal to
ground, but with the gate held at d.c. ground through $L_1$ the device cannot carry 2 mA
unless its source sits at $-V_{GS} = -3.0$ V. The current source is therefore taken to
return to a negative rail, as is conventional in this style of drawing; nothing in parts
(a) to (c) depends on the choice, because $C_2$ places the source at a.c. ground either
way.