Question 2 of 5: Series–Shunt Feedback Amplifier — Feedback Factor, Design Ratio and Loop Gain
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams May 2018, 16-Elec-B5 Advanced
Electronics — 3 hours, CLOSED BOOK, one approved Casio or Sharp calculator. Five
questions, all to be answered, 20 marks each (100 marks total). In schematics ground
and chassis are common; op-amps are ideal and supply rails are ±15 V unless stated
otherwise. Candidates are told to state any interpretive assumption inside the answer, and to
supply block diagrams and schematics wherever an essay-format response needs them.
Reference texts. A. S. Sedra and K. C. Smith,
Microelectronic Circuits, 8th ed. (Ch. 7 transistor amplifiers, Ch. 8 differential and
multistage amplifiers, Ch. 10 frequency response, Ch. 11 feedback); B. Razavi,
Fundamentals of Microelectronics, 2nd ed. (Ch. 9 cascode stages — Question 5 is
its Example 9.9) and Design of Analog CMOS Integrated Circuits, 2nd ed. (Ch. 4
differential amplifiers, Ch. 6 frequency response); R. C. Jaeger and T. N. Blalock,
Microelectronic Circuit Design, 5th ed. (Ch. 17 low-frequency response); P. R. Gray,
P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed. (Ch. 8 feedback).
How each answer is laid out. Every question states its data,
the quantity sought, the circuit as drawn on the paper, a one-line strategy, then numbered
steps carrying the governing relation, the substitution and the intermediate result. Boxed
values are the answers a marker looks for, and each question closes with a results table and a
concept note.
Question 2: Series–Shunt Feedback Amplifier — Feedback Factor,
Design Ratio and Loop Gain (20 marks)
Given. A two-stage amplifier: $M_1$ is a common-source stage
loaded by $R_{D1}$ whose drain drives the gate of $M_2$; $M_2$ is a common-source stage loaded
by $R_{D2}$ whose drain is the output $v_O$. A resistive ladder returns from $v_O$ through
$R_2$ to the source of $M_1$, and $R_1$ runs from that source node to ground. The signal
$v_S$ (on a $V_{GG}$ pedestal) drives the gate of $M_1$. For part (d),
$g_{m1}=g_{m2}=4$ mA/V and $R_{D1}=R_{D2}=10$ kΩ; $r_{o1}$ and $r_{o2}$ are to be
neglected throughout.
Find. The feedback network and its $\beta$, the ideal
closed-loop gain, the ratio $R_2/R_1$ (and $R_2$) for an ideal gain of 10 V/V, an expression
for the loop gain $A\beta$, and the numerical values of $A$, $A\beta$ and $A_f$.
Question 2 — two-stage series–shunt (voltage-series) feedback amplifier. R1 and R2 sample the output voltage and return a fraction of it to the source of M1, in series with the gate drive.
Approach. Recognise the topology as voltage-series
(series–shunt), lift the $R_1$–$R_2$ ladder out as a two-port to read off $\beta$
and the loading it imposes, then evaluate the loaded open-loop gain stage by stage and close
the loop with $A_f = A/(1+A\beta)$.
The β network of Question 2, lifted out of the amplifier: a plain resistive divider driven by vO and returning vf, so β = R1/(R1+R2). Its loading on the amplifier is R1∥R2 in series with the source of M1, and R1+R2 shunting the output.
Part (a) — identify the topology and the feedback network. The
ladder $R_2$–$R_1$ connects across the output node and returns to the
source of $M_1$, not to its gate. Because it bridges the output node it
samples the output voltage (shunt sampling), and because the returned voltage
appears in series with the gate–source loop of $M_1$ it subtracts from $v_S$ in
series (series mixing). That is voltage-series, i.e. series–shunt feedback: the ideal
voltage amplifier, whose input resistance is raised and output resistance lowered by the
loop. The $\beta$ circuit is therefore just the two resistors.
Write the feedback factor. The ladder is driven by $v_O$ and, with the
gate current of a MOSFET zero, is unloaded at its own output, so it is a plain voltage
divider:
$$\beta=\frac{v_f}{v_O}=\frac{R_1}{R_1+R_2}$$
with $v_f$ the voltage fed back to the source of $M_1$. Note that $\beta$ here is
dimensionless because both the sampled and the mixed quantities are voltages — a
property of this topology alone.
State the ideal or upper-bound closed-loop gain. When the loop gain is
large, $A_f=A/(1+A\beta)\to 1/\beta$, so
$$A_f\big|_{\text{ideal}}=\frac{1}{\beta}=1+\frac{R_2}{R_1}$$
This is an upper bound and not an equality: a real, finite $A$ always leaves $A_f$ a little
below $1/\beta$. It is also why the closed-loop gain is set by a resistor ratio, which
matches and tracks on an integrated circuit far better than any device parameter.
Part (b) — solve the design ratio. Setting the ideal gain to
10 V/V,
$$1+\frac{R_2}{R_1}=10\quad\Longrightarrow\quad \boxed{\frac{R_2}{R_1}=9}$$
and with the stated $R_1=1$ kΩ this gives $\boxed{R_2 = 9\ \text{k}\Omega}$. Both
values are carried into part (d).
Part (c) — load the amplifier with the feedback network before writing
$A$. The $\beta$ network is not weightless: in the two-port method its loading is
applied to the basic amplifier before the loop is closed. Looking into the ladder from the
source of $M_1$ with the output shorted gives $R_1\parallel R_2$ in series with that
source; looking in from the output node with the input port open (series mixing draws no
current) gives $R_1+R_2$ shunting the drain of $M_2$. Hence the loaded open-loop gain
$$A=\underbrace{\frac{-g_{m1}R_{D1}}{1+g_{m1}(R_1\parallel R_2)}}_{\text{stage 1,
degenerated}}\times\underbrace{\Big[-g_{m2}\big(R_{D2}\parallel(R_1+R_2)\big)\Big]}
_{\text{stage 2, loaded}}$$
Write the loop gain. Multiplying by the feedback factor gives the
expression the question asks for:
$$A\beta=\frac{g_{m1}g_{m2}\,R_{D1}\big(R_{D2}\parallel(R_1+R_2)\big)}
{1+g_{m1}(R_1\parallel R_2)}\cdot\frac{R_1}{R_1+R_2}$$
Two inversions make $A$ positive, which is what a stable negative-feedback loop requires
with this (subtracting) mixing arrangement — a sign check worth doing before
substituting numbers.
Part (d) — evaluate the loading terms. With $R_1=1$ kΩ and
$R_2=9$ kΩ,
$$\begin{aligned}R_1\parallel R_2&=\frac{(1)(9)}{1+9}=0.9\ \text{k}\Omega\\
R_1+R_2&=10\ \text{k}\Omega\\
R_{D2}\parallel(R_1+R_2)&=10\parallel10=5\ \text{k}\Omega\end{aligned}$$
The degeneration term is the one that does the damage: $g_{m1}(R_1\parallel R_2)
=(4\times10^{-3})(900)=3.6$, so the first stage keeps only $1/4.6$ of its undegenerated
gain.
Evaluate the two stage gains and the open-loop gain. Substituting,
$$\begin{aligned}A_1&=\frac{-(4\times10^{-3})(10\times10^{3})}{1+3.6}
=\frac{-40}{4.6}=-8.696\\
A_2&=-(4\times10^{-3})(5\times10^{3})=-20.0\end{aligned}$$
so that $$\boxed{A=A_1A_2=(-8.696)(-20.0)=173.9\ \text{V/V}}$$
For comparison, ignoring the feedback network’s loading altogether would give
$g_{m1}R_{D1}\cdot g_{m2}R_{D2}=1600$ — nine times too large, and the single most
common error on this question.
Close the loop. With $\beta=1/10=0.1$,
$$A\beta=(173.9)(0.1)=\boxed{17.39},\qquad
A_f=\frac{A}{1+A\beta}=\frac{173.9}{18.39}=\boxed{9.456\ \text{V/V}}$$
The amount of feedback is $1+A\beta=18.39$, i.e. 25.3 dB of desensitivity.
Check the result against the design target and against an exact solve.
The realised 9.456 V/V sits 5.4 per cent below the ideal 10 V/V, which is exactly what a
loop gain of only 17.4 predicts — the fractional shortfall is $1/(1+A\beta)=5.4$ per
cent, so the two numbers confirm one another. Solving the three-node small-signal circuit
directly (source of $M_1$, drain of $M_1$, output), with no feedback formalism at all,
returns $v_O/v_S=9.458$, confirming the two-port bookkeeping to four figures.
Check — what “neglect $r_o$” buys and what
it costs. The question instructs that $r_{o1}$ and $r_{o2}$ be neglected, which is what
makes the closed forms above exact. In a real design $r_{o2}$ appears in parallel with
$R_{D2}\parallel(R_1+R_2)$ and would reduce $A$, hence $A\beta$, hence push $A_f$ a little
further below 10 V/V. The remedy is the standard one and worth a sentence in an exam answer:
raise the loop gain (more $g_m$ or a larger $R_{D1}$) until the shortfall is inside the
tolerance the specification allows.
Quantity
Result
Feedback network
$R_1$–$R_2$ voltage divider (voltage-series topology)