NivaarExam PrepOfficial exam papers ↗

22-Elec-B5 Advanced Electronics · May 2018

Question 3 of 5: Common-Emitter Amplifier — Sizing $C_{C1}$, $C_{C2}$ and $C_E$ for a 100 Hz Lower Corner

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams May 2018, 16-Elec-B5 Advanced Electronics — 3 hours, CLOSED BOOK, one approved Casio or Sharp calculator. Five questions, all to be answered, 20 marks each (100 marks total). In schematics ground and chassis are common; op-amps are ideal and supply rails are ±15 V unless stated otherwise. Candidates are told to state any interpretive assumption inside the answer, and to supply block diagrams and schematics wherever an essay-format response needs them.

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (Ch. 7 transistor amplifiers, Ch. 8 differential and multistage amplifiers, Ch. 10 frequency response, Ch. 11 feedback); B. Razavi, Fundamentals of Microelectronics, 2nd ed. (Ch. 9 cascode stages — Question 5 is its Example 9.9) and Design of Analog CMOS Integrated Circuits, 2nd ed. (Ch. 4 differential amplifiers, Ch. 6 frequency response); R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 5th ed. (Ch. 17 low-frequency response); P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed. (Ch. 8 feedback).

How each answer is laid out. Every question states its data, the quantity sought, the circuit as drawn on the paper, a one-line strategy, then numbered steps carrying the governing relation, the substitution and the intermediate result. Boxed values are the answers a marker looks for, and each question closes with a results table and a concept note.

Question 3: Common-Emitter Amplifier — Sizing $C_{C1}$, $C_{C2}$ and $C_E$ for a 100 Hz Lower Corner (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

QuantitySymbolValue
Upper bias resistor$R_{B1}$180 kΩ
Lower bias resistor$R_{B2}$270 kΩ
Source resistance$R_S$5 kΩ
Collector resistor$R_C$8 kΩ
Emitter resistor$R_E$2 kΩ
Load resistor$R_L$5 kΩ
Current gain$\beta$100
Transconductance$g_m$40 mA/V
Input resistance$r_\pi$2.5 kΩ
Target lower corner$f_L$100 Hz

Find. Values for the two coupling capacitors and the emitter bypass capacitor that place the amplifier’s lower −3 dB corner at 100 Hz, and a statement of which of the three governs that corner.

Q1+VCCRB1RCRB2CC2vORLRECECC1RSvS
Question 3 — common-emitter stage with the three capacitors that set the low-frequency corner: the two coupling capacitors CC1 and CC2 and the emitter bypass capacitor CE.

Approach. Use the method of short-circuit time constants: find the resistance each capacitor sees with the other two shorted, allocate the target $\omega_L$ between the three poles as a stated design choice, then invert $\omega=1/(RC)$ for each capacitor.

  1. Settle the value of $r_\pi$ before anything else. The paper prints “$r_\pi = 2.5\ 5$ kΩ”, which is ambiguous. The paper’s own data resolve it: $r_\pi=\beta/g_m=100/(40\times10^{-3})=2.5$ kΩ, so the intended value is 2.5 kΩ and the stray digit is a misprint. The implied bias current follows as $I_C=g_m V_T=(40\times10^{-3})(25\times10^{-3})=1$ mA, consistent with the “already biased properly” statement.
  2. Reduce the bias network. At signal frequencies $R_{B1}$ and $R_{B2}$ both terminate on a.c. ground, so they appear in parallel at the base: $$R_B=R_{B1}\parallel R_{B2}=\frac{(180)(270)}{180+270}=108\ \text{k}\Omega$$ and the base node presents $R_B\parallel r_\pi=108\parallel2.5=2.443$ kΩ — dominated by $r_\pi$, since the bias network is deliberately made stiff.
  3. Find the resistance seen by the input coupling capacitor. Short $C_{C2}$ and $C_E$, look out of $C_{C1}$’s own terminals, and the series path is the source resistance plus the amplifier’s input resistance: $$R_{C_{C1}}=R_S+(R_B\parallel r_\pi)=5000+2443=7.443\ \text{k}\Omega$$
  4. Find the resistance seen by the output coupling capacitor. With $C_E$ shorted the transistor is a current source, so looking out of $C_{C2}$ the collector side contributes $R_C$ and the load side $R_L$, in series: $$R_{C_{C2}}=R_C+R_L=8+5=13\ \text{k}\Omega$$
  5. Find the resistance seen by the bypass capacitor. This is the one that matters, because looking into the emitter of a BJT is looking into a very low resistance. With both coupling capacitors shorted, the resistance seen at the emitter node is $R_E$ in parallel with the resistance looking into the emitter itself: $$R_{C_E}=R_E\left\Vert\frac{r_\pi+(R_S\parallel R_B)}{\beta+1}\right. =2000\left\Vert\frac{2500+4779}{101}\right.=2000\parallel72.07$$ which gives $R_{C_E}=69.56\ \Omega$. That is two orders of magnitude smaller than either coupling resistance, which already answers the last part of the question.
  6. State the allocation, because the problem is under-determined. One specification and three unknowns admits infinitely many solutions, so the split must be declared as a design choice. The defensible convention places the two coupling poles a decade below the target, where they contribute little, and lets the emitter capacitor carry the remainder: $$f_{C_{C1}}=f_{C_{C2}}=10\ \text{Hz}\ (10\ \%\ \text{each}),\qquad f_{C_E}=80\ \text{Hz}\ (80\ \%)$$ In $\omega$ terms, $\omega_L=2\pi(100)=628.3$ rad/s split as $62.83+62.83+502.6$ rad/s.
  7. Invert each time constant. With $C=1/(R\,\omega)$ for each pole, $$\begin{aligned}C_{C1}&=\frac{1}{(7443)(62.83)}=2.14\ \mu\text{F}\\ C_{C2}&=\frac{1}{(13000)(62.83)}=1.224\ \mu\text{F}\\ C_E&=\frac{1}{(69.56)(502.6)}=28.6\ \mu\text{F}\end{aligned}$$ Recombining, $\left(1/R_{C_{C1}}C_{C1}+1/R_{C_{C2}}C_{C2}+1/R_{C_E}C_E\right)/2\pi$ returns exactly 100 Hz, which is the arithmetic check on all three at once.
  8. Answer the “which dominates” part explicitly. The emitter bypass capacitor dominates, and structurally rather than because of the allocation chosen. It sees 69.56 Ω against 7.4 kΩ and 13 kΩ, a factor of roughly 150, so for any sensible split it is both the largest capacitor and the one whose pole sits closest to $f_L$. Even if all three poles were placed identically, $C_E$ would still come out around two orders of magnitude larger than the coupling capacitors.
  9. Round to stock values on the safe side. Capacitors come in E12 steps, and a lower corner is safe when it lands below the specification, which means rounding every capacitance up. Taking $$C_{C1}=2.2\ \mu\text{F},\qquad C_{C2}=1.2\ \mu\text{F},\qquad C_E=33\ \mu\text{F}$$ the recombined estimate becomes $\boxed{f_L = 89.3\ \text{Hz}}$, comfortably inside the 100 Hz requirement. (The 1.2 µF is a rounding down of 1.224 µF, but it moves the total by under 0.2 Hz because that pole carries only a tenth of the corner.)
  10. Check the estimate against an exact solve. The sum-of-time-constants method over-estimates $f_L$ whenever the poles are not widely separated, so it errs conservatively. Solving the full four-node low-frequency network with the three designed capacitances and bisecting for the half-power point gives an exact corner of 90.1 Hz against the 100 Hz the method predicts — about 11 per cent optimistic, and in the safe direction. The midband gain of the design is $|A_v|=g_m(R_C\parallel R_L)\dfrac{R_B\parallel r_\pi}{R_S+R_B\parallel r_\pi}=40.4$ V/V (32.1 dB), which is the reference level those corners are 3 dB below.

Check — the allocation is a stated choice, not a derived result. The 10/10/80 per cent split above is declared, not deduced; any split summing to $\omega_L$ is legitimate. Two common alternatives and their consequences: assigning the whole corner to $C_E$ and making the coupling capacitors “large” gives $C_E=22.9$ µF with $C_{C1}$ and $C_{C2}$ unconstrained, while splitting $\omega_L$ evenly in three gives $C_E=68.6$ µF. The convention used here keeps the two coupling capacitors to sensible physical sizes while leaving a clearly dominant pole, which is what makes the final answer easy to sanity-check.

QuantityResult
$R_B = R_{B1}\parallel R_{B2}$108 kΩ
Resistance seen by $C_{C1}$7.443 kΩ
Resistance seen by $C_{C2}$13 kΩ
Resistance seen by $C_E$69.56 Ω
$C_{C1}$ (computed / E12)2.14 µF / 2.2 µF
$C_{C2}$ (computed / E12)1.224 µF / 1.2 µF
$C_E$ (computed / E12)28.6 µF / 33 µF
Dominant capacitor$C_E$ — it sees only 69.6 Ω
Realised $f_L$ (E12 values, SCTC estimate)89.3 Hz
Realised $f_L$ (exact four-node solve, designed values)90.1 Hz
Midband gain40.4 V/V (32.1 dB)