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23-Mechatronics-A2 Circuits and Electronics: December 2019

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Ladder network — equivalent resistance and branch voltage
  2. Question 2 Node-voltage equations with a dependent source
  3. Question 3 First-order RC switching transient
  4. Question 4 AC bridge — Thévenin equivalent and maximum power transfer
  5. Question 5 Superposition in an AC parallel network
  6. Question 6 Second-order series RLC switching, Laplace-domain solution
  7. Question 7 Part B — Electronics
  8. Question 8 Part B, Question 2: Common-source MOSFET amplifier — bias design and gain
  9. Question 9 Part B, Question 3: Slew-rate-limited unity-gain follower
  10. Question 10 Part B, Question 4: CMOS inverter voltage transfer characteristic
  11. Question 11 Part B, Question 5: Op-amp/diode circuits — output waveform sketches

Start with Question 1 →

Paper: National Exams, December 2019 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics, Questions (1)–(5); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.

Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first- and second-order transients, AC phasor analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — diode limiters, MOSFET biasing and small-signal gain, op-amp slew rate, and CMOS inverter VTC.

Reading the figures. Every network below is redrawn element-by-element from the printed figures. Part B Question 1’s diode/zener network is analysed as the standard bidirectional bridge limiter (current is routed through the same pair of forward diodes for either output polarity, with the zener idle in the direct path); this is flagged as an engineering assumption below since the printed figure does not resolve current directions unambiguously. Part B Question 4 (CMOS inverter VTC) is answered symbolically in terms of the given threshold voltages, since the question supplies no device transconductance parameters.

Part A — Circuits