23-Mechatronics-A2 Circuits and Electronics · December 2019
Question 3 of 11: First-order RC switching transient
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper: National Exams, December 2019 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics, Questions (1)–(5); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.
Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first- and second-order transients, AC phasor analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — diode limiters, MOSFET biasing and small-signal gain, op-amp slew rate, and CMOS inverter VTC.
Reading the figures. Every network below is redrawn element-by-element from the printed figures. Part B Question 1’s diode/zener network is analysed as the standard bidirectional bridge limiter (current is routed through the same pair of forward diodes for either output polarity, with the zener idle in the direct path); this is flagged as an engineering assumption below since the printed figure does not resolve current directions unambiguously. Part B Question 4 (CMOS inverter VTC) is answered symbolically in terms of the given threshold voltages, since the question supplies no device transconductance parameters.
Switch-shunted resistor $R_{sw}$ (bypassed while switch is closed)
5 Ω
Resistor in parallel with $C$
2 Ω
Series resistor to source return
3 Ω
Capacitance $C$
0.5 F
Find. $v_c(0^+)$, $\dfrac{dv_c}{dt}(0^+)$, $i_c(0^+)$, $v_c(\infty)$, and $v_c(t)$ for $t\ge0$.
Figure-3: 25 V dc source in series with a switch-shunted 5 Ω resistor (switch closed → 5 Ω bypassed; open at $t=0$ → 5 Ω active), feeding a node where a 2 Ω resistor and 0.5 F capacitor are in parallel, then a 3 Ω resistor back to the source.
Approach. Find the pre-switch steady state for continuity of $v_c$, then use the post-switch Thévenin equivalent seen by the capacitor for the transient.
Steady state before switching. The closed switch shorts $R_{sw}$, so the capacitor (open at dc) sees only the 2 Ω and 3 Ω resistors in series: $I=\frac{25}{2+3}=5\ \text{A}$, so $$v_c(0^-)=I\times2=10.0\ \text{V}=v_c(0^+)\ (\text{continuity}),\ \boxed{v_c(0^+)=10.0\ \text{V}}.$$
Currents at $t=0^+$ (switch now open, $R_{sw}$ active, $v_c$ unchanged at 10.0 V). Writing node KCL at the two internal nodes (source current in through $R_{sw}$ equals the return current out through the 3 Ω resistor, since the 2 Ω branch and $C$ are the only path between them) and solving gives $$i_c(0^+)=\boxed{-3.1250\ \text{A}}\ (\text{negative}=\text{discharging}),\qquad \frac{dv_c}{dt}(0^+)=\frac{i_c(0^+)}{C}=\boxed{-6.2500\ \text{V/s}}.$$
Final value. As $t\to\infty$ the capacitor is again open, so $$v_c(\infty)=E\cdot\frac{2}{R_{sw}+2+3}=25\times\frac{2}{10}=\boxed{5.0\ \text{V}}.$$
Thévenin resistance and time constant. Killing $E$, the capacitor sees $2\|(R_{sw}+3)=2\|8=1.600\ \Omega$, so $$\tau=R_{th}C=1.600\times0.5=0.800\ \text{s}.$$
Assemble $v_c(t)$. $$v_c(t)=5.0+5.0\,e^{-t/0.80}\ \text{V},\quad t\ge0,$$ i.e. $\boxed{v_c(t)=5.0+5.0e^{-1.25t}\ \text{V}}$. Check: slope at $t=0$ is $-5.0/0.80=-6.250\ \text{V/s}$, matching Step 2.
