Part B, Question 4: CMOS inverter voltage transfer characteristic: 23-Mechatronics-A2 Circuits and Electronics, December 2019, Q10

Part B, Question 4: CMOS inverter voltage transfer characteristic [20]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A CMOS inverter (PMOS $M_2$ from $V_{DD}$ to the output, NMOS $M_1$ from the output to ground, gates tied together as $v_{IN}$) with symbolic thresholds $V_{Tn}$ (NMOS) and $|V_{Tp}|$ (PMOS); no numeric transconductance parameters are supplied, so the VTC is derived symbolically.

Find. The five-region VTC shape with $V_{OH},V_{OL},V_{IL},V_{IH}$ labelled, the noise margins $NM_L,NM_H$, and the operating region (cutoff/triode/saturation) of each transistor in every segment.

CMOS inverter VTC (schematic, not to scale): flat at $V_{DD}$ for $v_I<V_{Tn}$, a shallow decline through $V_{IL}$, a steep transition through the switching threshold $V_M$ (both transistors saturated), a shallow decline through $V_{IH}$, then flat at 0 for $v_I>V_{DD}-|V_{Tp}|$.

Approach. Track which of the two transistors is in cutoff, triode, or saturation as $v_I$ sweeps from 0 to $V_{DD}$; the five resulting combinations are the five VTC segments, and $V_{IL},V_{IH}$ are defined as the two points where the local slope is exactly $-1$.

Region A ($0\le v_I<V_{Tn}$). NMOS $M_1$ is cut off (no channel), PMOS $M_2$ is deep in triode (its $|V_{GS}|=V_{DD}-v_I$ is large). No current flows, so $$v_O=V_{DD}=\boxed{V_{OH}}.$$
Region B ($V_{Tn}\le v_I\le V_{IL}$). $M_1$ turns on and enters saturation; $M_2$ remains in triode. $v_O$ begins to fall, but the slope magnitude is still <1.
Region C (around the switching threshold $V_M$, from $V_{IL}$ to $V_{IH}$). Both transistors are in saturation simultaneously; because both devices offer high incremental output resistance here, a small change in $v_I$ produces a very large change in $v_O$ — the near-vertical drop through $V_M$ (defined by $i_{Dn}=i_{Dp}$). $V_{IL}$ and $V_{IH}$ are, by definition, the two edges of this steep segment where $dv_O/dv_I=-1$ exactly.
Region D ($V_{IH}\le v_I\le V_{DD}-|V_{Tp}|$). $M_1$ is now in triode, $M_2$ in saturation; $v_O$ continues down but with slope magnitude <1 again.
Region E ($v_I>V_{DD}-|V_{Tp}|$). $M_2$ cuts off ($|V_{GS,p}|<|V_{Tp}|$), $M_1$ is deep in triode, and $$v_O=0=\boxed{V_{OL}}.$$
Noise margins. By definition $$NM_L=V_{IL}-V_{OL}=\boxed{V_{IL}},\qquad NM_H=V_{OH}-V_{IH}=\boxed{V_{DD}-V_{IH}}.$$

Quantity	Result
$V_{OH}$	$V_{DD}$ (region A, $M_1$ cutoff)
$V_{OL}$	0 (region E, $M_2$ cutoff)
$V_{IL},V_{IH}$	edges of the near-vertical segment, $dv_O/dv_I=-1$
$NM_L$	$V_{IL}-V_{OL}=V_{IL}$
$NM_H$	$V_{OH}-V_{IH}=V_{DD}-V_{IH}$
Region order (increasing $v_I$)	cutoff/triode → sat/triode → sat/sat → triode/sat → triode/cutoff

Concept & Theory

Topic. CMOS inverter five-region VTC.

Key relations. NMOS/PMOS square-law saturation and triode equations; region boundaries at $v_I=V_{Tn}$ and $v_I=V_{DD}-|V_{Tp}|$; switching threshold from $i_{Dn}=i_{Dp}$ with both in saturation; $V_{IL},V_{IH}$ from $dv_O/dv_I=-1$.

Why this works. CMOS achieves rail-to-rail logic levels and zero static current because exactly one transistor is always cut off at each rail-side extreme; the steep transition region exists precisely where both devices are simultaneously in their high-gain saturation region, which is also why CMOS gates switch with high noise immunity — the transition is compressed into a narrow band of $v_I$ rather than spread gradually across the whole supply range.

Common pitfall. Confusing $V_{IL}/V_{IH}$ (defined by unity-slope points on the VTC) with the transistor threshold voltages $V_{Tn}/V_{Tp}$ (which only mark where each device individually turns on); assuming $V_M=V_{DD}/2$ without stating that this requires matched transistor strengths ($k_n=k_p$).

Source. Sedra & Smith, Microelectronic Circuits §10.1–10.3 (CMOS inverter VTC, noise margins).

Question 10 of 11: Part B, Question 4: CMOS inverter voltage transfer characteristic

Part A — Circuits

Part B, Question 4: CMOS inverter voltage transfer characteristic [20]