23-Mechatronics-A2 Circuits and Electronics · December 2019
Question 5 of 11: Superposition in an AC parallel network
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper: National Exams, December 2019 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics, Questions (1)–(5); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.
Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first- and second-order transients, AC phasor analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — diode limiters, MOSFET biasing and small-signal gain, op-amp slew rate, and CMOS inverter VTC.
Reading the figures. Every network below is redrawn element-by-element from the printed figures. Part B Question 1’s diode/zener network is analysed as the standard bidirectional bridge limiter (current is routed through the same pair of forward diodes for either output polarity, with the zener idle in the direct path); this is flagged as an engineering assumption below since the printed figure does not resolve current directions unambiguously. Part B Question 4 (CMOS inverter VTC) is answered symbolically in terms of the given threshold voltages, since the question supplies no device transconductance parameters.
Part A — Circuits
Question 5: Superposition in an AC parallel network [20]
Figure-5: all elements in parallel between the same two rails — current source $i_s$, $10\,\Omega$, $0.5$ F capacitor ($V_o$ across it), $2$ H inductor, and voltage source $V_s$ (+ at top).
Approach. Apply each source alone (the other killed) and sum — but first check whether any source dominates the output node directly.
$V_s$ acting alone (current source open-circuited). $V_s$ is connected directly across the same two rails as $V_o$, with no series impedance between them, so $$V_o^{(V_s)}(t)=V_s(t)=10\sin(20t)\ \text{V}.$$
$i_s$ acting alone (voltage source killed — replaced by a short). Killing $V_s$ places an ideal short directly across the very same two rails that $V_o$ is measured on, forcing $$V_o^{(i_s)}(t)=0\ \text{V}$$ regardless of $i_s$, $R$, $L$, or $C$ — none of that current can develop a voltage across a short.
Cross-check. Direct nodal analysis of the full circuit confirms the same result: an ideal voltage source in parallel with a node is a hard constraint that fixes that node’s voltage exactly, independent of whatever current sources or impedances also terminate there — $R$, $L$, and $i_s$ only affect how much current $V_s$ itself must supply, never $V_o$.