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23-Mechatronics-A2 Circuits and Electronics · December 2019

Question 11 of 11: Part B, Question 5: Op-amp/diode circuits — output waveform sketches

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper: National Exams, December 2019 — 16-Mex-A2 Circuits and Electronics. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Two parts: Part A — Circuits (Q1–Q6) and Part B — Electronics, Questions (1)–(5); candidates normally answer 5 of the 11 questions (3+2 or 2+3 split). Full worked solutions to all eleven questions are given below so the set can be used for study regardless of which five a candidate chose.

Reference texts: C. K. Alexander & M. N. O. Sadiku, Fundamentals of Electric Circuits (7th ed.) — resistive networks, superposition, Thévenin/max-power transfer, first- and second-order transients, AC phasor analysis; W. H. Hayt et al., Engineering Circuit Analysis (9th ed.) — Laplace-domain circuit models; A. S. Sedra & K. C. Smith, Microelectronic Circuits (8th ed.) — diode limiters, MOSFET biasing and small-signal gain, op-amp slew rate, and CMOS inverter VTC.

Reading the figures. Every network below is redrawn element-by-element from the printed figures. Part B Question 1’s diode/zener network is analysed as the standard bidirectional bridge limiter (current is routed through the same pair of forward diodes for either output polarity, with the zener idle in the direct path); this is flagged as an engineering assumption below since the printed figure does not resolve current directions unambiguously. Part B Question 4 (CMOS inverter VTC) is answered symbolically in terms of the given threshold voltages, since the question supplies no device transconductance parameters.

Part A — Circuits

Part B, Question 5: Op-amp/diode circuits — output waveform sketches [4,4,4,4,4]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Ideal diode drop 0.7 V; ideal op-amps, supplies $\pm15$ V; $v_{IN}=10\sin\theta$ V in every sub-circuit.

Find. $v_{OUT}(\theta)$ for one input cycle, for each of (a)–(e), with every clamp/saturation level identified.

(a)(b)(c)(d)(e)
Output waveforms (solid) against the input sine (dashed) for sub-circuits (a)–(e). Each panel is drawn to its own vertical scale.

Approach. In every sub-circuit the inverting input is a virtual ground (0 V) as long as the negative-feedback resistor is present; find the diode’s conduction condition at that virtual ground, evaluate the linear (diode-off) transfer function, and check the result against the $\pm15$ V supply rails.

  1. (a) Diode clamps the negative output. Diode anode is at the virtual ground (0 V), cathode at $v_{OUT}$; it conducts once $v_{OUT}<-0.7$ V. Diode off: $v_{OUT}=-\dfrac{5\text{k}}{5\text{k}}v_{IN}=-v_{IN}$, valid while $v_{IN}\le0.7$ V. $$\boxed{v_{OUT}=-v_{IN}\ (v_{IN}\le0.7\text{V}),\qquad v_{OUT}=-0.7\text{V (clamped)}\ (v_{IN}>0.7\text{V}).}$$ Peaks reach $+10$ V (well inside the rails), no saturation.
  2. (b) Diode clamps the positive output; op-amp also saturates. The 2 kΩ resistor sits between the virtual ground and true ground — both its ends are at 0 V, so it carries no current and has no effect. Diode (cathode at virtual ground, anode at $v_{OUT}$) conducts once $v_{OUT}>0.7$ V, i.e. once $v_{IN}<-0.14$ V (from the diode-off gain $-5$). For $v_{IN}\ge-0.14$ V the unclamped $-5v_{IN}$ would run past $-15$ V once $v_{IN}>3$ V, so the op-amp itself saturates there: $$\boxed{v_{OUT}=+0.7\text{V}\ (v_{IN}<-0.14\text{V}),\quad -5v_{IN}\ (-0.14\le v_{IN}\le3\text{V}),\quad -15\text{V (saturated)}\ (v_{IN}>3\text{V}).}$$
  3. (c) Summing amp, diode clamps almost the whole cycle. Diode off gives $v_{OUT}=-3v_{IN}-30$; setting this to the $-0.7$ V clamp threshold gives $v_{IN}=-9.767$ V — only in the narrow window $-10\le v_{IN}\le-9.767$ V (near the input’s own trough) is the diode off. $$\boxed{v_{OUT}=-0.7\text{V for essentially the whole cycle}\ (v_{IN}>-9.767\text{V}),\ \text{rising briefly to }0\text{V at the trough}\ (v_{IN}=-10\text{V}).}$$
  4. (d) Summing amp, diode clamps the negative excursion, op-amp saturates the positive. Diode off: $v_{OUT}=-5v_{IN}-5$; conducts (clamps at $+0.7$ V) once $v_{IN}<-1.14$ V. The linear branch would exceed $-15$ V once $v_{IN}>2$ V, saturating the op-amp there: $$\boxed{v_{OUT}=+0.7\text{V}\ (v_{IN}<-1.14\text{V}),\quad -5v_{IN}-5\ (-1.14\le v_{IN}\le2\text{V}),\quad -15\text{V}\ (v_{IN}>2\text{V}).}$$
  5. (e) Plain inverting amp, gain limited only by the rails. $v_{OUT}=-3v_{IN}$ ideally, but this reaches $\pm30$ V for a $\pm10$ V input, saturating at $\pm15$ V once $|v_{IN}|>5$ V: $$\boxed{v_{OUT}=-3v_{IN}\ (|v_{IN}|\le5\text{V}),\qquad v_{OUT}=\mp15\text{V (saturated)}\ (v_{IN}\gtrless\pm5\text{V}).}$$ The output is a $\times3$-amplified sine flat-topped at both rails.
QuantityResult
(a)$-v_{IN}$, clamped at $-0.7$ V for $v_{IN}>0.7$ V
(b)$-5v_{IN}$, clamped at $+0.7$ V, saturates at $-15$ V beyond $v_{IN}=3$ V
(c)flat $-0.7$ V almost the entire cycle (diode off only very near the trough)
(d)clamped $+0.7$ V, linear $-5v_{IN}-5$, saturates $-15$ V beyond $v_{IN}=2$ V
(e)$-3v_{IN}$, saturates at $\mp15$ V beyond $|v_{IN}|=5$ V
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