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23-Mechatronics-A3 Digital Logic and Embedded Systems: December 2018

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Gate-level realisation of a Boolean function
  2. Question 2 Synchronous 3-bit JK-flip-flop counter
  3. Question 3 K-map minimisation and PAL/PLA implementation
  4. Question 4 Computer-system architecture and CPU registers
  5. Question 5 Big-endian byte storage and stack PUSH
  6. Question 6 Multiplexed 2-digit 7-segment LED display driver

Start with Question 1 →

Paper: National Exams, December 2018 — 16-Mex-A3 Digital Systems & Computers. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Candidates normally answer 5 of 6 questions; full worked solutions to all six are given below, whichever five a candidate chose.

Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean algebra and gate-level design (Ch. 2), combinational logic (Ch. 4), synchronous sequential logic, state tables and counters (Ch. 5), programmable logic (PAL/PLA, Ch. 7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU/memory/bus architecture, registers, addressing; Motorola/Freescale, M68HC11 Reference Manual — big-endian byte storage, stack push/pull, port-based I/O (the questions below use Motorola-style conventions throughout, as stated on the paper).

Reading the question. Q1’s function $g$ is printed with an overline whose exact grouping is partly ambiguous. This solution adopts the literal reading $g=\big(\overline{(A+B)\cdot\bar C}+B\bar C D\big)\cdot E\cdot(A+B)$, i.e. the complement bar covers the whole term $(A+B)\cdot\bar C$; every gate network below is verified by truth table against this reading. Per the instruction on the paper, none of the three realisations in (c)–(e) apply Boolean simplification to $g$ itself — they translate the expression as written, gate-for-gate.