23-Mechatronics-A3 Digital Logic and Embedded Systems · December 2018
Question 5 of 6: Big-endian byte storage and stack PUSH
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper: National Exams, December 2018 — 16-Mex-A3 Digital Systems & Computers. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Candidates normally answer 5 of 6 questions; full worked solutions to all six are given below, whichever five a candidate chose.
Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean algebra and gate-level design (Ch. 2), combinational logic (Ch. 4), synchronous sequential logic, state tables and counters (Ch. 5), programmable logic (PAL/PLA, Ch. 7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU/memory/bus architecture, registers, addressing; Motorola/Freescale, M68HC11 Reference Manual — big-endian byte storage, stack push/pull, port-based I/O (the questions below use Motorola-style conventions throughout, as stated on the paper).
Reading the question. Q1’s function $g$ is printed with an overline whose exact grouping is partly ambiguous. This solution adopts the literal reading $g=\big(\overline{(A+B)\cdot\bar C}+B\bar C D\big)\cdot E\cdot(A+B)$, i.e. the complement bar covers the whole term $(A+B)\cdot\bar C$; every gate network below is verified by truth table against this reading. Per the instruction on the paper, none of the three realisations in (c)–(e) apply Boolean simplification to $g$ itself — they translate the expression as written, gate-for-gate.
Given. 16-bit value to store/push: hex $7A01 $=0111\,1010\,0000\,0001_2$, i.e. high byte $7A, low byte $01. Big-endian convention: the more-significant byte is stored at the lower memory address. (a) target (named) address $C239, with neighbouring cells $C238 and $C23A shown for context. (b) SP = $DC51 before the push, stack occupies decreasing addresses, with neighbouring cells $DC50 and $DC52 shown.
Find. The byte written to each labelled cell in both memory diagrams, and SP after the push.
Approach. Split $7A01 into its high/low bytes, then place them per the stated addressing convention: for (a) a direct store, the named address is where the addressing mode "points," so big-endian places the MS byte there and the LS byte at address+1; for (b) a full-descending, SP-points-to-next-free-byte push (the standard Motorola stack model), each byte is written at the current SP and SP is then decremented, so the low byte (pushed first, into the pre-push SP location) ends up at the higher of the two used addresses and the high byte at the lower one — the same big-endian ordering as (a), just built by two decrementing single-byte writes instead of one two-byte store.
(a) Direct store to $C239. The instruction names $C239 as the store address, so (big-endian) the MS byte goes there and the LS byte at the next address: Mem[$C239] = $7A (MSB), Mem[$C23A] = $01 (LSB). $C238 lies below the target address and is untouched by this instruction — it is shown only to establish the "Low Memory" direction on the diagram.
(b) Push onto the stack, SP=$DC51 (next free byte, stack grows toward low memory). A 16-bit push writes the low byte first at the current SP, decrements SP, then writes the high byte at the new SP and decrements again: Mem[$DC51] = $01 (LSB, written first), SP ← $DC50; Mem[$DC50] = $7A (MSB), SP ← $DC4F. This reproduces the same big-endian layout as part (a) — MS byte at the lower of the two used addresses ($DC50), LS byte at the higher ($DC51) — and $DC52 (above the pre-push SP) is never touched, shown only for the "High Memory" direction.
(c) SP after the PUSH. Two bytes were written, each followed by a decrement: $$SP_{\text{after}}=\text{DC51}_{16}-2=\boxed{\text{DC4F}_{16}}.$$ (i.e. $DC4F)
Check. The exact micro-sequencing of a 16-bit PUSH (byte order, pre- vs. post-decrement) is architecture-specific and not stated on the paper; the sequence above follows the standard Motorola 6800/68HC11-family "SP points to the next free byte, full-descending stack" convention named in the question stem, and yields the same big-endian byte layout in memory as part (a) — the internally consistent reading.
