23-Mechatronics-A3 Digital Logic and Embedded Systems · December 2018
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Paper: National Exams, December 2018 — 16-Mex-A3 Digital Systems & Computers. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Candidates normally answer 5 of 6 questions; full worked solutions to all six are given below, whichever five a candidate chose.
Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean algebra and gate-level design (Ch. 2), combinational logic (Ch. 4), synchronous sequential logic, state tables and counters (Ch. 5), programmable logic (PAL/PLA, Ch. 7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU/memory/bus architecture, registers, addressing; Motorola/Freescale, M68HC11 Reference Manual — big-endian byte storage, stack push/pull, port-based I/O (the questions below use Motorola-style conventions throughout, as stated on the paper).
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Given. The 8-row truth table:
| X | Y | Z | A | B | C | D |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 |
Find. Minimal SOP for $A,B,C,D$, and the more suitable programmable-logic family for implementing all four simultaneously.
Approach. Plot each output on its own 3-variable K-map (rows $X{=}0/1$, columns $YZ$ in Gray-code order $00,01,11,10$), group adjacent 1s into the largest possible pairs/quads, then compare the resulting product terms across all four outputs to decide between PAL and PLA.
(a) K-map minimisation.
(b) PAL vs PLA. Collecting the distinct product terms actually needed: $A$ uses $\{YZ,\bar XZ,X\bar Y\bar Z\}$; $B$ uses $\{XY,XZ,YZ,\bar X\bar Y\bar Z\}$; $C$ uses $\{\bar Z,\bar XY\}$; $D$ uses $\{YZ,X\bar Y,\bar XY\}$. Two terms recur across outputs: $YZ$ (needed by $A$, $B$ and $D$) and $\bar XY$ (needed by $C$ and $D$). That is 12 term-uses collapsing to 9 distinct AND-plane rows.
A PAL has a programmable AND array but a fixed OR array — each output OR-gate is wired to its own dedicated block of AND rows, so a term shared between two outputs must be generated twice (once per output's private AND rows), i.e. a PAL implementation would need all 12 term-uses as separate AND gates. A PLA has both arrays programmable, so any one AND-plane row can be routed to any number of OR-gates: the 9 unique product terms above are generated once each and shared, giving a $9\times4$ PLA array (9 AND rows $\times$ 3 input literals, feeding 4 programmable OR gates) instead of 12 dedicated AND gates. $$\boxed{\text{PLA is the better choice here} - \text{term sharing ($YZ$, $\bar XY$) cuts the AND-plane from 12 to 9 rows.}}$$
| Output | Minimal SOP |
|---|---|
| $A$ | $\boxed{A=YZ+\bar XZ+X\bar Y\bar Z}$ |
| $B$ | $\boxed{B=XY+XZ+YZ+\bar X\bar Y\bar Z}$ |
| $C$ | $\boxed{C=\bar Z+\bar XY}$ |
| $D$ | $\boxed{D=YZ+X\bar Y+\bar XY}$ |
| Architecture | $\boxed{\text{PLA}}$ (9 shared AND rows vs. 12 for a PAL) |