Synchronous 3-bit JK-flip-flop counter: 23-Mechatronics-A3 Digital Logic and Embedded Systems, December 2018, Q2

Question 2: Synchronous 3-bit JK-flip-flop counter [6+3+3 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Target cycle (written $Q_AQ_BQ_C$): $000\to010\to100\to101\to011\to001\to000\ (\text{repeat})$ — 6 of the 8 possible states are used; $110$ and $111$ never occur by design and are don't-cares. Flip-flop excitation table (from the reference sheet): $Q\to Q^+{=}0$: $J{=}0,K{=}X$; $Q\to Q^+{=}1$: $J{=}1,K{=}X$; $Q{=}1\to Q^+{=}0$: $J{=}X,K{=}1$; $Q{=}1\to Q^+{=}1$: $J{=}X,K{=}0$.

Find. The state diagram, the full JK excitation table, minimised $J,K$ equations, the wired circuit, self-starting behaviour, and an 8-pulse timing diagram.

Approach. Standard synchronous design: draw the state diagram → tabulate present/next state → back out each flip-flop's required $J,K$ from the excitation table → K-map (with the two unused states as don't-cares) to minimise $J,K$ → wire the flip-flops and combinational logic → verify self-starting by evaluating the don't-care states with the chosen equations → simulate the timing.

Fig. 2(a)-i — state transition diagram: the designed 6-state cycle (solid) and the two unused states (dashed, evaluated in part (b)).

State transition table with flip-flop inputs. For each of the 6 used transitions, read $J,K$ per bit off the excitation table above:

$Q_AQ_BQ_C$	$Q_A^+Q_B^+Q_C^+$	$J_AK_A$	$J_BK_B$	$J_CK_C$
000	010	0,X	1,X	0,X
010	100	1,X	X,1	0,X
100	101	X,0	0,X	1,X
101	011	X,1	1,X	X,0
011	001	0,X	X,1	X,0
001	000	0,X	0,X	X,1
110, 111	unused — all six J/K entries are don't-care (X)

K-map minimisation. Plotting each $J,K$ column over $A,B,C$ with the unused rows as don't-cares gives, after grouping: $$J_A=B\bar C,\quad K_A=C,\qquad J_B=A\odot C=AC+\bar A\bar C,\quad K_B=1,\qquad J_C=A,\quad K_C=\bar A\bar B.$$
Wire the circuit. Three JK flip-flops share a common clock and asynchronous $\overline{CLR}$. $K_A=Q_C$ and $J_C=Q_A$ are direct feedback wires; $J_A=Q_B\bar Q_C$ and $K_C=\bar Q_A\bar Q_B$ each need one 2-input gate; $J_B$ needs an XNOR (or AND-OR pair) of $Q_A,Q_C$; $K_B$ is tied permanently HIGH.

Fig. 2(a)-ii — final circuit: three JK flip-flops with the combinational $J/K$ logic derived above.

(b) Self-starting check. Evaluating the same $J,K$ equations at the two unused states (this is the only way to know where the don't-cares actually send the counter, since a K-map leaves that undefined until equations are chosen):

Unused state	Next state (from the equations above)	In the 6-state cycle?
110	101	Yes
111	001	Yes

Both unused states feed directly back into the valid cycle after a single clock pulse. $\boxed{\text{The counter is self-starting}}$ — no separate lock-up loop exists among $\{110,111\}$, so power-on noise or a glitch that lands the counter in an unused state recovers automatically within one clock cycle.

(c) Timing diagram. With $\overline{CLR}$ released just before $t=0$, all flip-flops are cleared, so the state at $t=0$ is $000$. Each rising CLK edge thereafter advances one step along the cycle:

Fig. 2(c) — CLK, $Q_A$, $Q_B$, $Q_C$ for 8 clock pulses, starting from $t=0=000$.

Quantity	Result
$J_A,K_A$	$\boxed{J_A=B\bar C,\ K_A=C}$
$J_B,K_B$	$\boxed{J_B=A\odot C,\ K_B=1}$
$J_C,K_C$	$\boxed{J_C=A,\ K_C=\bar A\bar B}$
Self-starting?	$\boxed{\text{Yes}}$ — $110\to101$, $111\to001$
State sequence over 8 pulses	$\boxed{010,100,101,011,001,000,010,100}$

Concept & Theory

Topic. Synchronous sequential-circuit design with JK flip-flops; self-starting analysis of don't-care states.

Key relations. JK excitation table (four rows above); characteristic equation $Q^+=J\bar Q+\bar KQ$; K-map minimisation with don't-cares.

Why this works. The JK excitation table inverts the flip-flop's characteristic equation: instead of asking "given $J,K$, what is $Q^+$", it asks "given the required $Q\to Q^+$ transition, what $J,K$ produce it" — and because JK has a genuine don't-care input combination for both $0\to0$ and $1\to1$, sequential design with JKs almost always yields simpler equations than with D or T flip-flops. Self-starting is never guaranteed by the K-map alone: don't-cares are filled in to minimise logic, and only plugging the resulting equations back in for the unused states reveals whether they loop into the main cycle or form an isolated trap.

Common pitfall. Declaring a counter self-starting just because "don't cares were used" — the actual destination of each unused state depends on which SOP the K-map produced, and must be checked explicitly, as done in part (b).

Source. Mano & Ciletti, Digital Design §5.3–5.6 (sequential circuit analysis/design, JK excitation, state diagrams) and §6.3 (counter design).

Question 2 of 6: Synchronous 3-bit JK-flip-flop counter

Question 2: Synchronous 3-bit JK-flip-flop counter [6+3+3 = 12]