NivaarExam PrepOfficial exam papers ↗

23-Mechatronics-A3 Digital Logic and Embedded Systems · December 2018

Question 4 of 6: Computer-system architecture and CPU registers

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper: National Exams, December 2018 — 16-Mex-A3 Digital Systems & Computers. Closed-book, 3-hour paper (approved Casio/Sharp calculator only). Candidates normally answer 5 of 6 questions; full worked solutions to all six are given below, whichever five a candidate chose.

Reference texts: M. M. Mano & M. D. Ciletti, Digital Design (6th ed.) — Boolean algebra and gate-level design (Ch. 2), combinational logic (Ch. 4), synchronous sequential logic, state tables and counters (Ch. 5), programmable logic (PAL/PLA, Ch. 7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems (6th ed.) — CPU/memory/bus architecture, registers, addressing; Motorola/Freescale, M68HC11 Reference Manual — big-endian byte storage, stack push/pull, port-based I/O (the questions below use Motorola-style conventions throughout, as stated on the paper).

Reading the question. Q1’s function $g$ is printed with an overline whose exact grouping is partly ambiguous. This solution adopts the literal reading $g=\big(\overline{(A+B)\cdot\bar C}+B\bar C D\big)\cdot E\cdot(A+B)$, i.e. the complement bar covers the whole term $(A+B)\cdot\bar C$; every gate network below is verified by truth table against this reading. Per the instruction on the paper, none of the three realisations in (c)–(e) apply Boolean simplification to $g$ itself — they translate the expression as written, gate-for-gate.

Question 4: Computer-system architecture and CPU registers [4+4+4 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

(a) The four essential components. A computer system, at the architectural level taught for this exam, is built from exactly four functional blocks: a unit that executes instructions, a unit that holds instructions/data, a unit that moves information in and out, and the interconnect that ties them together.

ItemEssential?
Mouse—
Busses (address, data, control)X
Processor (CPU)X
Keyboard—
Printer—
Display monitor—
Hard drive—
I/O portsX
MemoryX

$\boxed{\text{CPU, Memory, I/O ports, and the Busses}}$ are the four essential components. Mouse, keyboard, printer, monitor and hard drive are all specific peripheral instances of the generic "I/O ports" (or, for the hard drive, mass-storage) category — useful, but not themselves one of the four architectural blocks; a computer can run (e.g. an embedded controller) with none of those five attached.

(b) Microprocessor vs. microcontroller. A general-purpose microprocessor (e.g. an x86 or ARM applications CPU) is a bare execution unit on a single chip: it has no on-chip program or data memory and no built-in I/O, so a usable system needs external RAM/ROM chips, address decoding logic, and separate I/O/peripheral chips (UART, timer, ADC) wired onto a board. It is optimised for raw computational throughput and is used inside general-purpose computers that run varied, user-loaded software.

A microcontroller (e.g. an HC11/HC12 or an 8051) integrates the CPU core together with program memory (Flash/ROM), data memory (RAM), I/O ports, timers/counters and often an ADC and serial interface, all on one chip — a complete "computer on a chip." It sacrifices peak computational power and address space for low cost, low power, small board area, and self-sufficiency, and it is optimised for embedded, single-purpose control tasks (running one fixed program) rather than general-purpose computing.

(c) Register mapping.

RoleRegister
Address of the next instruction to be executed$\boxed{\text{Program Counter (PC)}}$
Next available location at the top of the stack$\boxed{\text{Stack Pointer (SP)}}$
Pointing to an array or list of data values in memory$\boxed{\text{Index register (IX/IY)}}$
Decision-making information for conditional branches$\boxed{\text{Condition Code / Status (Flags) Register}}$