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22-Elec-A4 Digital Systems and Computers · Undated paper

Question 2 of 6: Synchronous up/down counter with JK flip-flops (12 pts)

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. National Exams, 22-Elec-A4 — Digital Systems and Computers. Closed book; non-programmable calculator permitted; 3 hours. Six questions, each worth 12 points; “any five constitute a complete paper,” so all six are solved here as a study resource.

Reference texts. M. M. Mano & M. D. Ciletti, Digital Design, 5th/6th ed. (Pearson) — K-maps, hazards, PLA/PAL, flip-flop excitation and synchronous-counter design (ch. 3–6); J. F. Wakerly, Digital Design: Principles and Practices (static hazards, memory decoding); Motorola/Freescale M68HC11 Reference Manual (address decoding and memory-mapped I/O for Q5). Boolean identities and the flip-flop excitation tables printed on the exam cover sheet are used throughout.

Note on the figures. Where a single wire or junction in the Q4 figure is genuinely ambiguous, the reading used is stated and the alternative is flagged in a check callout, per the exam’s own instruction to “submit a clear statement of any assumptions made.”

Question 2 — Synchronous up/down counter with JK flip-flops (12 pts)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Two state bits $AB$ ($A$ = MSB), enable $E$ and direction $X$. The $E=1,X=1$ sequence is the binary up count and $E=1,X=0$ is the binary down count; $E=0$ freezes the state. The JK excitation table is $0\!\to\!0:J{=}0,K{=}\!\times$; $0\!\to\!1:J{=}1,K{=}\!\times$; $1\!\to\!0:J{=}\!\times,K{=}1$; $1\!\to\!1:J{=}\!\times,K{=}0$.

Find. $J_A,K_A,J_B,K_B$ as functions of $A,B,E,X$, and the resulting diagram, table and gate circuit.

Q2(a) state diagram (edge label = E X)11111111101010100-0-0-0-00011011
(a) State diagram. Edge label $=EX$: “$11$” = enabled up, “$10$” = enabled down, “$0{-}$” = hold ($E=0$).

Approach. Recognise the specification as an enabled up/down counter ($X$ = direction), tabulate the next state, read the JK excitations, and minimise.

  1. (b) State/excitation table. With $s=2A+B$, the next state is $s$ (hold) for $E=0$, $(s{+}1)\bmod4$ for $E{=}1,X{=}1$, and $(s{-}1)\bmod4$ for $E{=}1,X{=}0$. Reading the JK table for each bit gives the excitations below.
  2. State/excitation table ($\times$ = don’t care)
    $E$$X$$A\,B$$A^{+}B^{+}$$J_A$$K_A$$J_B$$K_B$
    0–anyhold0000
    1100010×1×
    1101101××1
    111011×01×
    111100×1×1
    1000111×1×
    101110×0×1
    101001×11×
    1001000××1
  3. (c) K-map simplification. Bit $B$ toggles on every enabled clock in both directions, so $J_B=K_B=E$. Bit $A$ toggles only on the carry ($B{=}1$ while counting up) or the borrow ($B{=}0$ while counting down), i.e. when $B\odot X$ (equal); the enable $E$ multiplies every term. Hence$$\boxed{J_A=K_A=E\,(B\odot X)=E\,(BX+\overline B\,\overline X)\qquad J_B=K_B=E}$$The common factor $E$ realises the hold with $J{=}K{=}0$ — there is no need to gate the clock.
  4. (d) Circuit. One XNOR forms $B\odot X$; one AND gates it with $E$ to drive $J_A$ and $K_A$ (tied together); $E$ drives $J_B$ and $K_B$ directly. Both flip-flops share the clock.
AJKQQ'BJKQQ'EXB⊙XE·(B⊙X)ECLK to both flip-flops (E gates J,K so E=0 holds)
(d) Resulting logic circuit: $J_A{=}K_A{=}E(B\odot X)$ and $J_B{=}K_B{=}E$.
Question 2 excitation logic
InputExpression
$J_A=K_A$$E\,(BX+\overline B\,\overline X)$
$J_B=K_B$$E$