22-Elec-A4 Digital Systems and Computers · Undated paper
Question 3 of 6: Multi-output logic and PLA implementation (12 pts)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, 22-Elec-A4 — Digital Systems and Computers. Closed book; non-programmable calculator permitted; 3 hours. Six questions, each worth 12 points; “any five constitute a complete paper,” so all six are solved here as a study resource.
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design, 5th/6th ed. (Pearson) — K-maps, hazards, PLA/PAL, flip-flop excitation and synchronous-counter design (ch. 3–6); J. F. Wakerly, Digital Design: Principles and Practices (static hazards, memory decoding); Motorola/Freescale M68HC11 Reference Manual (address decoding and memory-mapped I/O for Q5). Boolean identities and the flip-flop excitation tables printed on the exam cover sheet are used throughout.
Note on the figures. Where a single wire or junction in the Q4 figure is genuinely ambiguous, the reading used is stated and the alternative is flagged in a check callout, per the exam’s own instruction to “submit a clear statement of any assumptions made.”
Question 3 — Multi-output logic and PLA implementation (12 pts)
Given. The 3-input, 4-output truth table (from the source; note the source text says “4-output” and the table indeed lists four outputs $X,Y,Z,W$):
Given truth table ($A$ = MSB)
$A$
$B$
$C$
$X$
$Y$
$Z$
$W$
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
Find. Minimal SoP for each output, then a PLA program (shared product terms in the AND plane, output sums in the OR plane).
Approach. Minimise each output on its own 3-variable map, then collect the distinct product terms so they can be shared across outputs in the AND plane.
(a) One K-map per output.
(a) Minimal expressions. Grouping the 1-cells of each map:$$X=BC^{\,\prime}+AB,\quad Y=\overline A\,\overline B+AB+C,\quad Z=\overline A\,\overline B+\overline B C,\quad W=\overline A+\overline B C+B\overline C$$Note $Y=(A\odot B)+C$ and $W=\overline A+(B\oplus C)$ are compact readings of the same covers.
Collect distinct product terms. Across the four outputs the product terms used are $\{\,BC^{\,\prime},\,AB,\,\overline A\,\overline B,\,C,\,\overline B C,\,\overline A\,\}$ — six distinct AND terms.
(b) PLA program. Six AND-plane rows feed the four OR-plane columns: $X=BC^{\,\prime}\!+\!AB$; $Y=\overline A\,\overline B\!+\!AB\!+\!C$; $Z=\overline A\,\overline B\!+\!\overline B C$; $W=\overline A\!+\!\overline B C\!+\!B\overline C$. The shared terms ($\overline A\,\overline B$ feeds $Y,Z$; $AB$ feeds $X,Y$; $\overline B C$ feeds $Z,W$) are what make the PLA (programmable AND and OR planes) more economical than four separate gate networks — a $3\times6\times4$ PLA suffices.
(b) PLA map: blue = AND-plane connections (literals per product term), red = OR-plane connections (product terms per output). 6 product terms, 4 outputs.
