22-Elec-A4 Digital Systems and Computers · Undated paper
Question 4 of 6: Analysis of an RS + T flip-flop circuit (12 pts)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, 22-Elec-A4 — Digital Systems and Computers. Closed book; non-programmable calculator permitted; 3 hours. Six questions, each worth 12 points; “any five constitute a complete paper,” so all six are solved here as a study resource.
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design, 5th/6th ed. (Pearson) — K-maps, hazards, PLA/PAL, flip-flop excitation and synchronous-counter design (ch. 3–6); J. F. Wakerly, Digital Design: Principles and Practices (static hazards, memory decoding); Motorola/Freescale M68HC11 Reference Manual (address decoding and memory-mapped I/O for Q5). Boolean identities and the flip-flop excitation tables printed on the exam cover sheet are used throughout.
Note on the figures. Where a single wire or junction in the Q4 figure is genuinely ambiguous, the reading used is stated and the alternative is flagged in a check callout, per the exam’s own instruction to “submit a clear statement of any assumptions made.”
Question 4 — Analysis of an RS + T flip-flop circuit (12 pts)
[Figure not reproduced: given figure. See the official exam paper or the cited reference text.]
Given circuit (cleaned crop of the source drawing): RS flip-flop $A$, T flip-flop $B$, input $X$, output $Y$.
Check — reading of the gate wiring. Several junctions of the printed circuit cannot be resolved with certainty. The reading used here is the one that is electrically valid ($R_A\!\cdot\!S_A=0$ at every reachable state) and self-consistent with the unambiguous gates: the top-left AND gate forms $X\!\cdot\!A$ and feeds the output OR (so $Y$ contains the input $X$), the right-hand OR gate forms $T_B$, and the RS gates factor as $A$ / $\overline A$ so that $A$ behaves as a toggle. If instead the output gate were read as a lone AND ($Y=AB$) the method and the (a)–(c) machinery are unchanged; only the Moore/Mealy verdict of (d) flips. The analysis below states the equations explicitly so the reader can re-map any single corrected wire.
Given. An RS flip-flop $A$ and a T flip-flop $B$ clocked together, with the gate network of the figure. Find. The input equations, the transition table, the state diagram, and the machine type.
Approach. Read the flip-flop input equations from the gates, apply each flip-flop’s characteristic equation ($A^{+}=S_A+\overline{R_A}A$ for RS, $B^{+}=T_B\oplus B$ for T), tabulate, then classify by whether $Y$ depends on the input.
(a) Input/output equations. From the gates: $$R_A=A\,(X+B),\quad S_A=\overline A\,(X+B),\quad T_B=X+A,\quad Y=X A+AB=A\,(X+B)$$ Since $R_A$ carries the factor $A$ and $S_A$ the factor $\overline A$, $R_A\!\cdot\!S_A=0$ automatically for every input — the forbidden RS state never occurs.
Characteristic equations. RS: $A^{+}=S_A+\overline{R_A}\,A =\overline A(X+B)+A\,\overline{(X+B)}=A\oplus(X+B)$. T: $B^{+}=T_B\oplus B=(X+A)\oplus B$. So both bits toggle — $A$ when $X+B$, $B$ when $X+A$.
(b) Transition table. Evaluating for the eight $(A,B,X)$ rows:
State transition table
$A$
$B$
$X$
$R_A$
$S_A$
$T_B$
$A^{+}$
$B^{+}$
$Y$
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
0
1
(c) State diagram. Below, with Mealy labelling $X/Y$.
(c) State transition diagram (Mealy: edge label $=X/Y$).
(d) Moore or Mealy? The output $Y=XA+AB=A(X+B)$ contains the primary input $X$: in state $AB=10$, $Y=0$ when $X=0$ but $Y=1$ when $X=1$. Because the output is a function of the input as well as the present state, this is a Mealy machine (its output can change between clock edges when $X$ changes). Had the output depended only on $A,B$ it would be Moore — see the check callout.
