64 KB memory from 16K×4 modules (12 pts): 22-Elec-A4 Digital Systems and Computers, Undated paper, Q6

Question 6 — 64 KB memory from 16K×4 modules (12 pts)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

[Figure not reproduced: given figure. See the official exam paper or the cited reference text.]

Given figure (cleaned crop): the CPU with a 16-line address bus and 8-line data bus feeding column-paired memory modules (a 4th column is implied by the dashed continuation).

Check — module width. The prose specifies 16K×4 modules while every box in the drawing is lettered “16K×8.” The drawn topology settles it: modules are paired two-per-column sharing one $\overline{CS}$, which is width expansion and is only meaningful for ×4 parts (one nibble each). We therefore solve to the prose (16K×4); the box legend is a typo in the printed figure, per the exam’s “state any assumptions” rubric.

Given. An 8-bit CPU, 16-line address bus $A_{15}\!-\!A_0$, 8-line data bus $D_7\!-\!D_0$, and 16K×4 modules ($2^{14}=16\,384$ locations, 4 data bits each). Find. Bus/line assignments, the $\overline{CS}$ decode logic, and each module’s address range.

Approach. A 64 KB, 8-bit space needs $64\text{K}/16\text{K}=4$ banks (depth) each $8/4=2$ modules wide $\Rightarrow 8$ modules. Bits $A_{13}\!-\!A_0$ address a bank internally; $A_{15},A_{14}$ select the bank via a 2:4 decoder.

(a) Line assignments. Each 16K×4 module: address pins $A_{13}\!-\!A_0$ (14 lines, the “$A$” blanks $=13\ldots0$); data pins split by column — the top module carries $D_7\!-\!D_4$ and the bottom module $D_3\!-\!D_0$ (the “$D$” blanks). Address-bus width $=16$, data-bus width $=8$.
(b) Chip-select logic. Feed $A_{15}$ (MSB) and $A_{14}$ into a 2:4 decoder with active-low outputs; each output drives the shared $\overline{CS}$ of both modules in one column: $$\overline{CS_0}=\overline{\overline{A_{15}}\,\overline{A_{14}}},\quad \overline{CS_1}=\overline{\overline{A_{15}}\,A_{14}},\quad \overline{CS_2}=\overline{A_{15}\,\overline{A_{14}}},\quad \overline{CS_3}=\overline{A_{15}\,A_{14}}$$ $A_{15},A_{14}$ are decoded (not the internal address) because each bank spans exactly the 16 KB selected by the low 14 lines.
(c) Address ranges. With $A_{13}\!-\!A_0$ spanning 0–3FFFh inside each bank:

(a)–(c) Bank map: four banks of two 16K×4 modules (top nibble $D_7\!-\!D_4$, bottom nibble $D_3\!-\!D_0$), selected by $A_{15}A_{14}$.

Question 6 memory map
Bank (2 modules)	$A_{15}A_{14}$	Address range	$\overline{CS}$
0	00	0000h – 3FFFh	$\overline{\overline{A_{15}}\,\overline{A_{14}}}$
1	01	4000h – 7FFFh	$\overline{\overline{A_{15}}\,A_{14}}$
2	10	8000h – BFFFh	$\overline{A_{15}\,\overline{A_{14}}}$
3	11	C000h – FFFFh	$\overline{A_{15}\,A_{14}}$

Question 6 of 6: 64 KB memory from 16K×4 modules (12 pts)

Question 6 — 64 KB memory from 16K×4 modules (12 pts)