22-Elec-A4 Digital Systems and Computers · Undated paper
Question 5 of 6: HC11 memory-mapped I/O routing (12 pts)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, 22-Elec-A4 — Digital Systems and Computers. Closed book; non-programmable calculator permitted; 3 hours. Six questions, each worth 12 points; “any five constitute a complete paper,” so all six are solved here as a study resource.
Reference texts. M. M. Mano & M. D. Ciletti, Digital Design, 5th/6th ed. (Pearson) — K-maps, hazards, PLA/PAL, flip-flop excitation and synchronous-counter design (ch. 3–6); J. F. Wakerly, Digital Design: Principles and Practices (static hazards, memory decoding); Motorola/Freescale M68HC11 Reference Manual (address decoding and memory-mapped I/O for Q5). Boolean identities and the flip-flop excitation tables printed on the exam cover sheet are used throughout.
Note on the figures. Where a single wire or junction in the Q4 figure is genuinely ambiguous, the reading used is stated and the alternative is flagged in a check callout, per the exam’s own instruction to “submit a clear statement of any assumptions made.”
[Figure not reproduced: given figure. See the official exam paper or the cited reference text.]
Given schematic (cleaned crop): the decoder output $\overline{Y_2}$ clocks the D flip-flop; $Q$ closes switch 1 (HOST), $\overline Q$ closes switch 2 (MCU).
Given. Decoder inputs $A_{15}A_{14}A_{13}$ (MSB…LSB); the tapped active-low output is $\overline{Y_2}$ (verified against the printed paper — it is the third output, not $\overline{Y_0}$ as the raw extraction suggested), so the flip-flop is clocked only by a store whose address gives $A_{15}A_{14}A_{13}=010$. On that clock edge $Q$ captures $D_0$ of the stored byte; $Q=1$ closes switch 1 (HOST), $Q=0$ makes $\overline Q=1$ closing switch 2 (MCU).
Find. For each instruction pair, whether the store hits $\overline{Y_2}$ and, if so, the value of $D_0$.
Approach. Only $A_{15}A_{14}A_{13}$ of the store address and only bit $D_0$ of the accumulator value matter; the low address bits and the upper data bits are decoys. The band $A_{15}A_{14}A_{13}=010$ is the address range 4000h–5FFFh.
Identify the active band. $\overline{Y_2}$ is asserted for $A_{15}A_{14}A_{13}=010$, i.e. store addresses 4000h–5FFFh. A store outside this band toggles a different decoder output and leaves the flip-flop (hence the routing) unchanged.
(a) ldaa #$10, staa $8000. 8000h $=1000\,\ldots$, so $A_{15}A_{14}A_{13}=100\to\overline{Y_4}$, not $\overline{Y_2}$: the flip-flop is not clocked → No Action.
(b) ldaa #$29, staa $4000. 4000h $=0100\,\ldots\to A_{15}A_{14}A_{13}=010$, so $\overline{Y_2}$ clocks the flip-flop. $\mathtt{29}_{16}=0010\,1001_2$ has $D_0=1\Rightarrow Q=1$ → HOST computer I/O port.
(c) ldaa #$B4, staa $5000. 5000h $=0101\,\ldots\to A_{15}A_{14}A_{13}=010$: $\overline{Y_2}$ clocks the flip-flop. $\mathtt{B4}_{16}=1011\,0100_2$ has $D_0=0\Rightarrow Q=0$ → MCU I/O port.
(d) ldaa #$05, staa $2500. 2500h $=0010\,\ldots\to A_{15}A_{14}A_{13}=001\to\overline{Y_1}$, not $\overline{Y_2}$: the flip-flop is not clocked → No Action (the odd $D_0=1$ is irrelevant because no clock edge occurs).
