Feedback amplifier — input and output resistance: 22-Elec-B5 Advanced Electronics, May 2013, Q2

Question 2: Feedback amplifier — input and output resistance (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single n-channel MOSFET is driven at its source and delivers its output at the drain, where a drain resistor $R_{D}$ returns to $+V_{DD}$. A resistive divider $R_{1}$–$R_{2}$ hangs across the output and its tap drives the gate, so a fraction of $v_{OUT}$ is returned to the gate–source loop. Only the small-signal transconductance $g_{m}$ is specified; the channel-length modulation resistance $r_{o}$ and the body effect are not given and are taken as negligible.

Find. Closed-form expressions for the resistance seen looking into the input terminal at the source, $R_{IN}$, and the resistance seen looking back into the output node, $R_{OUT}$, first with the feedback network removed and then with $R_{1}$ and $R_{2}$ finite — in terms of $g_{m}$, $R_{D}$, $R_{1}$ and $R_{2}$ only.

Question 2 — a common-gate stage wrapped in voltage-series (series–shunt) feedback. The divider samples the output voltage and returns βv_OUT to the gate, in series with the input at the gate–source loop.

Approach. Write the two node equations exactly — the gate draws no current, so the divider is unloaded — solve for the driving-point resistances, and then re-read both answers in feedback language to expose the loop transmission.

Part (a) — remove the feedback and recognise a common-gate stage. Setting $R_{1}=\infty$ and $R_{2}=0$ ties the gate to ground, so the transistor is a plain common-gate amplifier driven at the source. A test voltage $v_{s}$ at the source produces $i_{d}=g_{m}v_{gs}=-g_{m}v_{s}$, and the current drawn from the test source is $g_{m}v_{s}$, so $$\boxed{R_{IN}=\frac{1}{g_{m}},\qquad R_{OUT}=R_{D}}$$ With $r_{o}$ neglected the drain is an ideal current source, so nothing but $R_{D}$ appears at the output. These two are the open-loop values that part (b) will modify.
Part (b) — write the exact node equations with the divider in place. Because the MOS gate draws no current, the divider is a simple unloaded potential divider across the output: $$v_{G}=\frac{R_{2}}{R_{1}+R_{2}}\,v_{OUT}\equiv\beta\, v_{OUT},\qquad \beta=\frac{R_{2}}{R_{1}+R_{2}} .$$ Seen from the drain node, the divider is simply a resistance $R_{1}+R_{2}$ to ground, so the total small-signal load there is $$R_{L}^{\prime}=R_{D}\parallel\left(R_{1}+R_{2}\right) =\frac{R_{D}\left(R_{1}+R_{2}\right)}{R_{D}+R_{1}+R_{2}} .$$
Solve for the input resistance. Drive the source terminal with a test voltage $v_{s}$ and let $i$ be the current it delivers. Since the drain current flows out of the source terminal, $i=-i_{d}=g_{m}\left(v_{s}-v_{G}\right)$, while KCL at the drain gives $g_{m}\left(v_{G}-v_{s}\right)=-v_{OUT}/R_{L}^{\prime}$. Eliminating $v_{OUT}$ with $v_{G}=\beta v_{OUT}$ and forming $v_{s}/i$: $$R_{IN}=\frac{1}{g_{m}}+\beta R_{L}^{\prime} =\frac{1}{g_{m}}+\frac{R_{2}}{R_{1}+R_{2}}\cdot \frac{R_{D}\left(R_{1}+R_{2}\right)}{R_{D}+R_{1}+R_{2}} ,$$ and the divider term collapses neatly, leaving $$\boxed{R_{IN}=\frac{1}{g_{m}}+\frac{R_{D}R_{2}}{R_{D}+R_{1}+R_{2}} =\frac{R_{D}+R_{1}+R_{2}+g_{m}R_{D}R_{2}}{g_{m}\left(R_{D}+R_{1}+R_{2}\right)}}$$ Setting $R_{2}=0$ recovers $1/g_{m}$, as it must.
Solve for the output resistance. Now ground the input, apply a test voltage $v$ at the output node and sum the currents leaving it: $v/R_{D}$ through the drain resistor, $v/(R_{1}+R_{2})$ through the divider, and $i_{d}=g_{m}v_{G}=g_{m}\beta v$ into the drain terminal. Hence $i=v\left(1/R_{L}^{\prime}+g_{m}\beta\right)$ and $$R_{OUT}=\frac{R_{L}^{\prime}}{1+g_{m}\beta R_{L}^{\prime}} \;\Longrightarrow\; \boxed{R_{OUT}=\frac{R_{D}\left(R_{1}+R_{2}\right)} {R_{D}+R_{1}+R_{2}+g_{m}R_{D}R_{2}}}$$ Again the check is immediate: with $R_{2}=0$ and $R_{1}\to\infty$ this reduces to $R_{D}$.
Read both results as a feedback transformation. Define the loop transmission of the single-loop amplifier as $$T=g_{m}\beta R_{L}^{\prime}=\frac{g_{m}R_{D}R_{2}}{R_{D}+R_{1}+R_{2}} .$$ Then the two boxed results are exactly $$R_{IN}=\frac{1}{g_{m}}\left(1+T\right),\qquad R_{OUT}=\frac{R_{L}^{\prime}}{1+T} ,$$ which identifies the topology: the divider samples the output voltage (shunt at the output) and returns it in series with the input in the gate–source loop. That is voltage-series — series–shunt — feedback, whose signature is precisely a series input resistance multiplied by $(1+T)$ and a shunt output resistance divided by $(1+T)$.

The design consequence is worth stating plainly: the same feedback that makes the drain node a stiffer voltage source makes the source terminal a harder load to drive. A designer who wants both a low output resistance and a low input resistance from this cell cannot get them from the same loop.

Question 2 — final results
Part	$R_{IN}$	$R_{OUT}$
(a) no feedback	$1/g_{m}$	$R_{D}$
(b) finite $R_{1},R_{2}$	$\dfrac{1}{g_{m}}+\dfrac{R_{D}R_{2}}{R_{D}+R_{1}+R_{2}}$	$\dfrac{R_{D}(R_{1}+R_{2})}{R_{D}+R_{1}+R_{2}+g_{m}R_{D}R_{2}}$
feedback form	$\left(1+T\right)/g_{m}$	$R_{L}^{\prime}/\left(1+T\right)$, $T=g_{m}R_{D}R_{2}/(R_{D}+R_{1}+R_{2})$

Topic. Identifying a feedback topology from a schematic and using it to predict how the closed loop transforms the terminal resistances.

Key relations. Feedback factor $\beta=R_{2}/(R_{1}+R_{2})$; loaded gain node $R_{L}^{\prime}=R_{D}\parallel(R_{1}+R_{2})$; loop transmission $T=g_{m}\beta R_{L}^{\prime}$; series mixing multiplies the input resistance by $(1+T)$; shunt sampling divides the output resistance by $(1+T)$; common-gate open-loop values $1/g_{m}$ and $R_{D}$.

Why this works. The four canonical feedback topologies are named by how the loop connects at each port, and the schematic tells you both at a glance. At the output the divider is wired across the load, so it senses voltage; at the input the returned signal appears at the gate while the drive appears at the source, so the two voltages subtract around the gate–source loop and the mixing is series. Series mixing means the loop opposes the input voltage, which forces the source to supply less current for the same drive, and that is what raises $R_{IN}$ by the loop factor. Shunt sensing means the loop opposes any change in the output voltage, which is exactly what a lower output resistance is. Solving the nodes exactly first, and only then recognising the pattern, is the safe order of work: it takes four lines, it never depends on correctly guessing the topology, and the feedback reading afterwards becomes a check rather than an assumption.

Common pitfall. Treating the divider as if it loaded the gate. It does not — an insulated MOS gate draws no current, so the divider is unloaded and the drain sees exactly $R_{1}+R_{2}$ in parallel with $R_{D}$. The second trap is applying the textbook formula $R_{in}=R_{in,\text{open}}(1+T)$ without noticing that the correct open-loop input resistance is the common-gate value $1/g_{m}$, not the infinite input resistance of a common-source stage; the input here is the source terminal, not the gate.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §11.1–11.4 (the general feedback structure and the four topologies), with the common-gate driving-point resistances from §7.5.

Question 2 of 6: Feedback amplifier — input and output resistance

Question 2: Feedback amplifier — input and output resistance (20 marks)