Question 4 of 6: Eight-bit analog-to-digital conversion — resolution and quantisation error
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
Paper format. National Exams, May 2013 — 07-Elec-B5
Advanced Electronics. Three hours, closed book; one approved
Casio or Sharp calculator is permitted. Six questions are printed and five (5)
constitute a complete paper — the first five appearing in the answer book
are marked — and every question is worth 20 marks. In schematics ground and chassis
may be assumed common; op-amps are ideal with ±15 V rails unless stated otherwise.
All six questions are solved here, because this set is a study resource
rather than a timed sitting.
Reference texts. A. S. Sedra, K. C. Smith, T. C. Carusone and
V. Gaudet, Microelectronic Circuits, 8th ed. — the recommended reference
for this exam code: Ch. 7 (transistor amplifiers and small-signal models), Ch. 8
(differential and multistage amplifiers), Ch. 10 (frequency response and the Miller
effect), Ch. 11 (feedback topologies and their resistance transformations), Ch. 12
(class-AB output stages) and Ch. 13 (data converters). Supplementary:
B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. (cascodes, CMRR,
tuned stages) and P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits, 5th ed.
Given. A unipolar converter with a full-scale range of
$V_{FSR}=10\ \text{V}$ (0 V to +10 V) and a word length of $n=8$ bits, giving
$2^{8}=256$ output codes. The converter is taken to be an ideal truncating quantiser, which
assigns to an input the largest code whose represented voltage does not exceed it.
Find. The resolution in volts; the 8-bit words representing 6 V and
6.2 V; the quantisation error at 6.2 V in volts, as a percentage of the input and
as a percentage of full scale; and the largest quantisation error the converter can make,
as a percentage of full scale.
Question 4 — detail of the transfer characteristic near 6.2 V. The staircase is the quantised output, the dashed diagonal the ideal characteristic; the vertical gap between them at any input is the quantisation error.
Approach. One step size sets everything: divide the full-scale
range by the number of codes, divide each input by that step and truncate to get the code,
then express the residue as a voltage and as the two required percentages.
Part (a) — divide the span by the number of codes. The
resolution, or least significant bit, is the voltage change that advances the output by one
code:
$$\boxed{V_{LSB}=\frac{V_{FSR}}{2^{n}}=\frac{10\ \text{V}}{256}=0.0390625\ \text{V}
=39.06\ \text{mV}}$$
Some texts define the resolution as $V_{FSR}/(2^{n}-1)=10/255=39.22\ \text{mV}$, the step
that makes the largest code correspond exactly to full scale. The difference is 0.4 % and,
as shown below, it changes neither of the two codes this question asks for; the
$2^{n}$ convention is used throughout.
Part (b) — convert 6 V to a code. Divide by the step and take the
integer part:
$$N=\left\lfloor\frac{6\ \text{V}}{0.0390625\ \text{V}}\right\rfloor
=\left\lfloor 153.6\right\rfloor=153 ,$$
and writing 153 in eight bits, $153=128+16+8+1$, gives
$$\boxed{6\ \text{V}\rightarrow N=153=1001\,1001_{2}}$$
which the converter reconstructs as $153\times0.0390625=5.9766\ \text{V}$. The alternative
$V_{FSR}/(2^{n}-1)$ scaling maps 6 V to exactly 153 as well, so the word is robust to
the convention.
Part (c) — convert 6.2 V to a code. The same operation gives
$$N=\left\lfloor\frac{6.2}{0.0390625}\right\rfloor=\left\lfloor 158.72\right\rfloor=158,
\qquad 158=128+16+8+4+2 ,$$
so
$$\boxed{6.2\ \text{V}\rightarrow N=158=1001\,1110_{2}}$$
represented as $158\times0.0390625=6.171875\ \text{V}$. Once again the other resolution
convention gives $\lfloor158.1\rfloor=158$, the same word.
Part (d) — express the residue three ways. The quantisation error
is what the truncation threw away:
$$e=V_{in}-N V_{LSB}=6.2-6.171875=0.028125\ \text{V}=28.1\ \text{mV},$$
which is 0.72 of one LSB. Referred to the input and to full scale,
$$\frac{e}{V_{in}}=\frac{0.028125}{6.2}=0.454\ \text{per cent},\qquad
\frac{e}{V_{FSR}}=\frac{0.028125}{10}=0.281\ \text{per cent}.$$
$$\boxed{e=28.1\ \text{mV}=0.454\ \% \text{ of the input}=0.281\ \% \text{ of full scale}}$$
Note that the two percentages differ by the ratio $V_{FSR}/V_{in}=1.61$; quoting error
“as a percentage” without saying of what is meaningless in converter
specifications, which is precisely why the question asks for both.
Part (e) — bound the error over the whole range. With truncation
the error is always non-negative and always smaller than one step, because as soon as the
input reaches the next multiple of $V_{LSB}$ the code advances and the residue resets to
zero. The supremum is therefore one full LSB:
$$\boxed{e_{max}=V_{LSB}=39.06\ \text{mV}=\frac{1}{2^{n}}=0.391\ \% \text{ of full scale}}$$
consistent with part (d), whose 0.281 % sits below this bound. A converter that rounds
instead of truncating — equivalently, one whose comparator thresholds are offset by
half a step — has an error in the range $\pm\tfrac{1}{2}V_{LSB}$ and a worst case of
0.195 % of full scale, half as large. This half-LSB offset is standard practice and is the
figure usually quoted on a data sheet.
