Class-AB output stage inside error amplifiers: 22-Elec-B5 Advanced Electronics, May 2013, Q6

Question 6: Class-AB output stage inside error amplifiers (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A complementary common-source output pair — PMOS $M_{1}$ with its source at $+V_{DD}$ and NMOS $M_{2}$ with its source at ground — whose drains are joined at $v_{OUT}$ across the load $R_{L}$. Two error amplifiers of finite gain $\mu$ each compare $v_{IN}$ at their inverting input with $v_{OUT}$ at their non-inverting input and drive the gates $V_{G1}$ and $V_{G2}$. The devices are matched, both carry the quiescent current $I_{Q}$ with zero input, and the analysis is small-signal about that operating point, where both devices conduct.

Find. A closed-form expression for $v_{OUT}/v_{IN}$ in terms of $\mu$, the device transconductance and $R_{L}$; the gain that the arrangement is intended to deliver; and the error between the two.

Question 6 — class-AB output stage with two error amplifiers. Each amplifier drives one gate from the difference v_OUT − v_IN, so both devices push the output towards the input.

Approach. Express each gate voltage in terms of the error signal, write the small-signal current each device delivers into the output node, apply KCL, and solve for the closed-loop gain; then read the result as a loop transmission.

Part (a) — find the transconductance of each output device. With both devices carrying $I_{Q}$ at the quiescent point and $I_{D}=\tfrac{1}{2}K\left(V_{GS}-V_{T}\right)^{2}$, the overdrive is $V_{ov}=\sqrt{2I_{Q}/K}$ and $$g_{m}=KV_{ov}=\sqrt{2KI_{Q}} .$$ Because the devices are matched, $g_{m1}=g_{m2}=g_{m}$ — this is what allows the two halves to be added rather than tracked separately.
Write the gate voltages produced by the error amplifiers. Each amplifier takes $v_{OUT}$ at its non-inverting input and $v_{IN}$ at its inverting input, so $$v_{g1}=v_{g2}=\mu\left(v_{OUT}-v_{IN}\right)=-\mu\, v_{\varepsilon}, \qquad v_{\varepsilon}\equiv v_{IN}-v_{OUT}.$$ The sign convention is what makes the loop negative rather than positive: if $v_{OUT}$ sags below $v_{IN}$ then both gate voltages fall, which turns the PMOS on harder (its source-gate voltage rises) and the NMOS off, and both actions push the output back up.
Sum the two device currents at the output node. With its source at $+V_{DD}$, a signal ground, the PMOS delivers a current into the output node of $g_{m}v_{sg1}=-g_{m}v_{g1}$. With its source at ground, the NMOS removes $g_{m}v_{gs2}=g_{m}v_{g2}$ from the same node. KCL therefore gives $$-g_{m}v_{g1}-g_{m}v_{g2}=\frac{v_{OUT}}{R_{L}} \;\Longrightarrow\; 2\mu g_{m}\left(v_{IN}-v_{OUT}\right)=\frac{v_{OUT}}{R_{L}} .$$ Both devices push in the same direction, which is why the factor of two appears: at the quiescent point the stage has a total transconductance of $2g_{m}$, not $g_{m}$.
Solve for the closed-loop gain. Collecting $v_{OUT}$, $$v_{OUT}\left(1+2\mu g_{m}R_{L}\right)=2\mu g_{m}R_{L}\,v_{IN} \;\Longrightarrow\; \boxed{\frac{v_{OUT}}{v_{IN}}=\frac{2\mu g_{m}R_{L}}{1+2\mu g_{m}R_{L}} =\frac{T}{1+T},\qquad T=2\mu g_{m}R_{L}=2\mu R_{L}\sqrt{2KI_{Q}}}$$ where $T$ is the loop transmission. Written this way the result is recognisable at sight as the closed-loop gain of a unity-feedback amplifier of forward gain $T$.
Part (b) — state the expected gain. The whole point of wrapping the output devices in error amplifiers is to make $T$ large, and as $T\rightarrow\infty$ $$\boxed{\frac{v_{OUT}}{v_{IN}}\rightarrow1}$$ The stage is intended to be a unity-gain buffer: it supplies current to $R_{L}$ without changing the voltage. That is the correct expectation for a power output stage, whose job is current gain and low output resistance, not voltage gain.
Part (c) — quantify how far short of unity it falls. The gain error is the difference between the ideal unity gain and the actual gain: $$\varepsilon=1-\frac{v_{OUT}}{v_{IN}}=1-\frac{T}{1+T} \;\Longrightarrow\; \boxed{\varepsilon=\frac{1}{1+2\mu g_{m}R_{L}}\approx\frac{1}{2\mu g_{m}R_{L}} \quad\text{for }T\gg1}$$ Equivalently, and more usefully for design, the stage behaves as an ideal unity-gain source in series with an output resistance $$R_{OUT}=\frac{1}{2\mu g_{m}}\;\Longrightarrow\; \frac{v_{OUT}}{v_{IN}}=\frac{R_{L}}{R_{L}+R_{OUT}},$$ so the gain error is simply the potential-divider loss between $R_{OUT}$ and $R_{L}$. The error amplifiers reduce the bare $1/g_{m}$ of a source follower by the factor $2\mu$, which is exactly the claim made in the question’s own preamble. As a worked instance, with $\mu=100$, $K=4\ \text{mA/V}^{2}$, $I_{Q}=1\ \text{mA}$ and $R_{L}=50\ \Omega$, $g_{m}=\sqrt{2KI_{Q}}=2.83\ \text{mA/V}$, $R_{OUT}=1.77\ \Omega$ and the error is 3.4 %.

Two practical notes follow directly from the expression. The error depends on $R_{L}$, so a stage that meets its specification into 50 $\Omega$ will do worse into a lower impedance; and it depends on $I_{Q}$ only as $\sqrt{I_{Q}}$, so quadrupling the quiescent current — and the standing dissipation — only halves the error. Raising $\mu$ is by far the cheaper lever, subject to keeping the loop stable.

Question 6 — final results
Part	Quantity	Result
—	Device transconductance	$g_{m}=\sqrt{2KI_{Q}}$
—	Loop transmission	$T=2\mu g_{m}R_{L}=2\mu R_{L}\sqrt{2KI_{Q}}$
(a)	Voltage gain $v_{OUT}/v_{IN}$	$\dfrac{2\mu g_{m}R_{L}}{1+2\mu g_{m}R_{L}}$
(b)	Expected gain	Unity (a voltage buffer)
(c)	Gain error $\varepsilon$	$\dfrac{1}{1+2\mu g_{m}R_{L}}\approx\dfrac{1}{2\mu g_{m}R_{L}}$
(c)	Equivalent output resistance	$R_{OUT}=1/(2\mu g_{m})$

Topic. Feedback around a complementary class-AB output stage: closed-loop gain, gain error and the reduction of output resistance.

Key relations. $g_{m}=\sqrt{2KI_{Q}}$ for a square-law device; loop transmission $T=2\mu g_{m}R_{L}$; closed-loop gain $T/(1+T)$; gain error $1/(1+T)$; output resistance $R_{OUT}=1/(2\mu g_{m})$, against $1/g_{m}$ for an unassisted source follower.

Why this works. A source follower used as an output stage has an output resistance of $1/g_{m}$, and in a power stage that is far too high — it costs signal swing into a low-impedance load and, worse, it varies with instantaneous current, producing distortion. Enclosing the devices in an amplifier of gain $\mu$ attacks both problems at once, because negative feedback divides output resistance by the loop transmission and linearises whatever sits inside the loop. The class-AB bias is what makes the small-signal result as simple as it is: because both devices carry $I_{Q}$ at rest, both are conducting for small signals and their transconductances add, giving $2g_{m}$ and eliminating the crossover region that plagues a class-B stage. Driving the two gates from two separate amplifiers, rather than one, keeps each device inside its own local loop and preserves that behaviour as the signal grows and one device takes over from the other.

Common pitfall. Dropping the factor of two by analysing only one half of the output stage; the answer is then $\mu g_{m}R_{L}/(1+\mu g_{m}R_{L})$ and the output resistance is twice too large. The second trap is getting the feedback polarity backwards. Reason it out physically rather than from the drawing: the PMOS needs its gate to fall to deliver more current, the NMOS needs its gate to fall to sink less, so a single common gate drive of the same sign serves both, and that sign must be such that a drooping output pulls both gates down.

Source. Sedra & Smith, Microelectronic Circuits, 8th ed., §12.3–12.5 (class-AB output stages and the use of error amplifiers to reduce output resistance), with the feedback transformations of §11.4.

Question 6 of 6: Class-AB output stage inside error amplifiers

Question 6: Class-AB output stage inside error amplifiers (20 marks)