Paper format. National Exams May 2017 — 16-Elec-B6,
Integrated Circuit Engineering. Three hours, closed book, scientific
calculator permitted. Six questions are printed; any five constitute a
complete paper and the total is 100 marks. Formulae and constants are supplied
on the last page of the examination. All six questions are solved here, so
the paper can be used as a complete study resource.
Reference texts.
- J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated
Circuits: A Design Perspective, 2nd ed. — the standard reference for
this exam code (complementary CMOS, dynamic and NP-domino logic, C2MOS
and TSPC sequential elements, interconnect and supply-noise chapters).
- N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, 4th ed. — layout extraction, junction capacitance and
adder structures.
- S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis
and Design, 3rd ed. — MOS capacitance models and transmission-line
effects on chip.
- A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed.
— device-level background (body effect, pass-transistor levels).
In Fig. Q4.2 the gate lead of M4 ends at its own input terminal, labelled C, and is not connected to the internal node between M2 and M3. Q4-2 is solved on that reading.
