Question 1 of 6: Reflections on a Terminated On-Chip Transmission Line

Question 1: Reflections on a Terminated On-Chip Transmission Line (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Find. The voltage waveform at node 1 (the driver end) and at node 2 (the inverter input) over five one-way flight times, for each of the three source impedances, with every step level computed.

Approach. Because the line is lossless and the far end is open, the problem is pure bounce-diagram bookkeeping: compute the two reflection coefficients, launch the first wave through the resistive divider formed by $Z_s$ and $Z_o$, and then add each arriving wave (and, at node 1, the wave it immediately re-launches) to the running node voltage.

1. Write the two reflection coefficients. The formula supplied with the paper is $$\Gamma_V=\frac{Z_L-Z_o}{Z_L+Z_o}.$$ At the far end the CMOS gate presents $Z_L=\infty$, so dividing numerator and denominator by $Z_L$ gives $\Gamma_L=1$: an open circuit returns the incident voltage wave unchanged and with the same sign. At the near end the same expression applies with the source impedance in place of the load, giving $\Gamma_S=(Z_s-Z_o)/(Z_s+Z_o)$.
2. Launch the first forward wave. At $t=0^{+}$ the line looks like a resistor of value $Z_o$, so the step divides between $Z_s$ and that resistance: $$V_1^{+}=v_s\,\frac{Z_o}{Z_s+Z_o}.$$ This is the level that appears at node 1 the instant the source switches, and it is what travels toward node 2.
3. Apply the bookkeeping rule. The forward wave reaches node 2 at $t=\tau$; node 2 immediately shows the incident wave plus its reflection, i.e. it steps by $(1+\Gamma_L)V^{+}=2V^{+}$. The reflected wave arrives back at node 1 at $t=2\tau$, where node 1 steps by $(1+\Gamma_S)$ times that wave, and $\Gamma_S$ times it sets off again. Each subsequent round trip therefore multiplies the travelling wave by $\Gamma_S\Gamma_L=\Gamma_S$, so the sequence is geometric and the sum converges on the open-circuit steady state $v_s=1$ V (no DC current flows, so no DC drop appears across $Z_s$).

Part (1) — matched source, $Z_s=Z_o$. Here $\Gamma_S=(Z_o-Z_o)/(Z_o+Z_o)=0$ and $V_1^{+}=1\times\tfrac{1}{2}=0.500$ V.

1. Node 1 holds the half-amplitude launch level for one round trip. From $t=0$ to $t=2\tau$, node 1 sits at $0.500$ V. At $t=2\tau$ the returning wave (also $0.500$ V) adds, and because $\Gamma_S=0$ nothing is re-launched: $$\boxed{v_1=0.500\ \text{V}\ (0\le t < 2\tau),\qquad v_1=1.000\ \text{V}\ (t\ge 2\tau).}$$
2. Node 2 reaches the final value in a single step. At $t=\tau$ the incident $0.500$ V and its reflection $0.500$ V arrive together, so node 2 jumps straight from 0 to $1.000$ V and stays there. A source-terminated line therefore delivers a clean, glitch-free full-swing edge to the gate after exactly one flight time — at the cost of the receiver waiting a full $\tau$ while node 1 sits at only half amplitude.

Part (2) — under-driven source, $Z_s=5Z_o$. Now $\Gamma_S=(5-1)/(5+1)=+2/3$ and the divider is weak, $V_1^{+}=1/(5+1)=1/6=0.1667$ V.

1. Tabulate the successive waves. Each round trip multiplies the travelling wave by $\Gamma_S=2/3$, so the forward waves are $\tfrac16,\ \tfrac19,\ \tfrac{2}{27},\dots$ Node 1 records the launch level, then at every even multiple of $\tau$ adds the returning wave and the wave it sends back out; node 2 records twice each arriving wave at every odd multiple of $\tau$.
2. Evaluate the levels inside the window. Working through the first three windows at each node gives the staircase below. Both nodes climb monotonically toward 1 V; nothing overshoots, because $\Gamma_S$ is positive.

   Interval	$v_1$ (V)	Interval	$v_2$ (V)
   $0\le t<2\tau$	$\tfrac16=0.1667$	$\tau\le t<3\tau$	$\tfrac13=0.3333$
   $2\tau\le t<4\tau$	$\tfrac49=0.4444$	$3\tau\le t<5\tau$	$\tfrac59=0.5556$
   $4\tau\le t<6\tau$	$\tfrac{17}{27}=0.6296$	$t\ge 5\tau$	$\tfrac{19}{27}=0.7037$

3. Read the design consequence. After five flight times the gate input has reached only $0.704$ V. With a 1 V supply that is close to the inverter switching threshold, so a large series source impedance makes the receiver wait several round trips before the logic level is unambiguous: $$\boxed{v_2(5\tau)=\tfrac{19}{27}=0.704\ \text{V},\ \text{still }29.6\%\ \text{short of the final value.}}$$

Part (3) — stiff source, $Z_s=Z_o/5$. Now $\Gamma_S=(0.2-1)/(0.2+1)=-2/3$, negative, and the divider is strong, $V_1^{+}=1/1.2=5/6=0.8333$ V.

1. Alternate the sign of each successive wave. Because $\Gamma_S$ is negative the forward waves alternate: $\tfrac56,\ -\tfrac59,\ \tfrac{10}{27},\dots$ The result is ringing about the final value rather than a monotonic climb.
2. Evaluate the levels inside the window. The same bookkeeping, with the alternating signs, gives the ringing sequence below.

   Interval	$v_1$ (V)	Interval	$v_2$ (V)
   $0\le t<2\tau$	$\tfrac56=0.8333$	$\tau\le t<3\tau$	$\tfrac53=1.6667$
   $2\tau\le t<4\tau$	$\tfrac{10}{9}=1.1111$	$3\tau\le t<5\tau$	$\tfrac59=0.5556$
   $4\tau\le t<6\tau$	$\tfrac{25}{27}=0.9259$	$t\ge 5\tau$	$\tfrac{35}{27}=1.2963$

3. Read the design consequence. The open far end doubles the incident wave, so node 2 overshoots to $$\boxed{v_2(\tau)=\tfrac53=1.667\ \text{V}=1.67\,v_s,}$$ then undershoots to $0.556$ V at $3\tau$ before ringing down. The undershoot is the dangerous one: it drags the gate input back below the switching threshold after it has already crossed it, producing a double transition on the inverter output. The overshoot is a reliability concern in its own right because it stresses the thin gate oxide of the receiving transistors.