Question 5 of 6: Pass-Transistor Levels, TSPC Sequencing and Simultaneous-Switching Noise

Question 5: Pass-Transistor Levels, TSPC Sequencing and Simultaneous-Switching Noise (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. In Fig.Q5.1 two nMOS pass transistors share the output node $V_{o1}$: the upper device has its gate on $B$ and passes $A$; the lower device has its gate on $\overline{B}$ and passes $B$. $V_{o1}$ drives a conventional static CMOS inverter whose output is $V_{o2}$, and $V_{TN}=|V_{TP}|=V_T$. Fig.Q5.2 is a three-stage TSPC cell driven by a single clock wire: stage 1 has a pMOS gated by $D$ in series with a pMOS gated by Clk above node $X$, and a single unclocked nMOS gated by $D$ below it; stage 2 is a dynamic gate precharged by a pMOS gated by Clk and evaluated through nMOS devices gated by $X$ and Clk, giving node $Y$; stage 3 has an unclocked pMOS gated by $Y$ pulling $\overline{Q}$ up and nMOS devices gated by Clk and $Y$ pulling it down. In Fig.Q5.3 the inverter's supply reaches the chip through a bond-wire inductance $L_{dd}$ and its ground through $L_{ss}$, and it drives a load capacitor $C_L$.

Find. The steady level at $V_{o1}$ for $A=B=V_{DD}$ and whether the following inverter burns static power; a demonstration that the TSPC cell samples on the rising clock edge; and sketches of $i_{CL}$, $V_{dd,\text{on-chip}}$ and $V_{ss,\text{on-chip}}$.

Approach. Part 1 is a pass-transistor level argument followed by an inspection of the inverter's bias point; part 2 is a phase-by-phase trace of the three dynamic nodes; part 3 follows from $i_C=C_L\,dv_o/dt$ and $v_L=L\,di/dt$.

Part 1(a) — the level at $V_{o1}$.

1. Confirm the function first. The upper device conducts when $B=1$ and passes $A$; the lower conducts when $B=0$ and passes $B$, which is 0. Hence $V_{o1}=B\cdot A+\overline{B}\cdot B=A\cdot B$, the AND2 the question names.
2. Follow the charging of the output node. With $A=B=V_{DD}$ the lower device is off ($\overline{B}=0$) and the upper device conducts with its gate at $V_{DD}$ and its drain held at $A=V_{DD}$. Current flows into $V_{o1}$ and stops the instant the device leaves conduction, which happens when its gate-to-source voltage falls to the threshold. Taking the output node as the source, $$V_{GS}=V_{DD}-V_{o1}=V_{TN}\quad\Longrightarrow\quad \boxed{V_{o1}=V_{DD}-V_{T}.}$$ Leakage of the reverse-biased junctions is neglected, so nothing discharges the node afterwards and it holds this degraded high indefinitely. With $V_{DD}=1.2$ V and $V_T=0.35$ V, for example, $V_{o1}=0.85$ V rather than 1.2 V — an nMOS passes a strong 0 and a weak 1, and no amount of extra time recovers the missing threshold.

Part 1(b) — static power in the following inverter.

1. Bias the two devices of the inverter. Its input is $V_{o1}=V_{DD}-V_T$. The nMOS sees $V_{GSn}=V_{DD}-V_T$, an overdrive of $V_{DD}-2V_T$ above its threshold, so it is firmly on. The pMOS sees $$|V_{GSp}|=V_{DD}-V_{o1}=V_{DD}-(V_{DD}-V_T)=V_T=|V_{TP}|,$$ i.e. it is biased exactly at its threshold rather than at the $|V_{GS}|=0$ that a full-swing input would give it.
2. Decide what that means for current. At $|V_{GS}|=|V_{TP}|$ a MOSFET is in weak inversion, where the drain current is exponential in gate voltage and is emphatically not zero — it is many orders of magnitude above the reverse junction leakage that the question tells us to neglect. With the nMOS strongly on at the same time, a continuous conducting path runs from $V_{DD}$ to ground: $$\boxed{\text{Yes: the inverter draws a static current, so }P_{static}=V_{DD}I_{static}\neq 0.}$$
3. Put the result in design context. This is the defining drawback of nMOS-only pass-transistor logic, and it is why CPL is always drawn with a level-restoring pMOS from $V_{DD}$ to $V_{o1}$ with its gate on $V_{o2}$. That feedback device pulls $V_{o1}$ the last $V_T$ up to the rail once the inverter has switched, turns the inverter's pMOS fully off, and eliminates the static path. The alternative is a transmission gate (an nMOS in parallel with a pMOS), which passes both levels without degradation at the cost of the complementary control signal.

Part 2 — the TSPC cell is positive edge triggered.

1. Trace the low phase, $\text{Clk}=0$. Stage 1's clocked pMOS conducts, so stage 1 is a complete static inverter and $X=\overline{D}$, tracking $D$ continuously. Stage 2's pMOS precharges $Y$ to $V_{DD}$ and its foot nMOS is off, so $Y=1$ whatever $X$ does. In stage 3, $Y=1$ turns its pMOS off and its clocked nMOS is off as well, so $\overline{Q}$ is high impedance and holds the previous output. Nothing at $D$ can reach the output while the clock is low.
2. Trace the rising edge. At the moment Clk goes high, stage 1 freezes the value $X=\overline{D}$ that $D$ had at the edge, because its clocked pull-up device switches off. Stage 2 now evaluates: if $X=1$ (that is, $D=0$ at the edge) the node $Y$ discharges to 0; if $X=0$ ($D=1$) the precharged $Y$ stays at 1. Hence $Y=\overline{X}=D$ as sampled at the edge. Stage 3 then resolves: $Y=1$ enables its clocked pull-down and $\overline{Q}$ goes to 0; $Y=0$ turns on its pMOS and $\overline{Q}$ goes to 1. So $$\boxed{\overline{Q}=\overline{D}\big|_{\text{at the rising edge}},\quad\text{i.e. }Q=D.}$$
3. Show that later changes of $D$ are ignored. This is the step that proves edge triggering rather than level sensitivity. While $\text{Clk}=1$ stage 1's pull-up is disabled, so $X$ can only be pulled low. Take $D=1$ at the edge, giving $X=0$: $X$ cannot rise, so $Y$ stays precharged at 1 and $\overline{Q}$ stays at 0 no matter what $D$ does. Take $D=0$ at the edge, giving $X=1$ and $Y$ already discharged to 0: if $D$ now goes to 1 then $X$ falls, but stage 2 has no pull-up available during $\text{Clk}=1$, so $Y$ holds 0 and $\overline{Q}$ holds 1. In both cases the output is insensitive to $D$ after the edge, which is exactly the definition of a positive edge-triggered D flip-flop.

Part 3 — the three sketched waveforms.

1. Capacitor current. With $i_{CL}$ taken as positive flowing from the output node into the load, $$i_{CL}=C_L\frac{dv_o}{dt}.$$ It is zero whenever $v_o$ is flat, so it is a pair of narrow spikes, one at each output transition, each decaying with the same time constant as the output edge. The output rises when $v_{in}$ falls, so that spike is positive and is supplied by the pMOS from $V_{dd,\text{on-chip}}$; the output falls when $v_{in}$ rises, so that spike is negative and is sunk by the nMOS into $V_{ss,\text{on-chip}}$. The peak magnitude is $C_L\,V_{DD}/\tau_{edge}$, which for a pad driver is tens of milliamperes.
2. On-chip supply. The supply current only flows through $L_{dd}$ during the charging transition, and $$V_{dd,\text{on-chip}}=V_{dd}-L_{dd}\frac{di_{dd}}{dt}.$$ On the rising edge of $v_o$ the current ramps up sharply, $di/dt>0$, and the on-chip supply dips below $V_{dd}$; as the current decays $di/dt$ reverses sign and the node overshoots. Because $L_{dd}$ resonates with the on-chip decoupling and well capacitance, the disturbance is a damped ringing at $f=1/(2\pi\sqrt{L_{dd}C_{dec}})$ rather than a single dip. Nothing happens on the discharging transition, when no current flows through $L_{dd}$.
3. On-chip ground. By the same argument with the sign reversed, $$V_{ss,\text{on-chip}}=L_{ss}\frac{di_{ss}}{dt},$$ so on the falling edge of $v_o$ the discharge current through $L_{ss}$ lifts the on-chip ground above the board ground — the classic ground bounce — and then rings down. This is the disturbance that corrupts the logic levels of neighbouring quiet gates, because their input thresholds are referred to the bounced on-chip rails: $$\boxed{\Delta V_{\text{noise}}=L\frac{di}{dt},\ \text{proportional to the number of drivers switching together.}}$$
4. Read the design consequence. Because the noise is proportional to $di/dt$ and to the number of simultaneously switching outputs, the standard remedies are on-chip decoupling capacitance, multiple supply and ground pads to lower the effective $L$, slew-rate-controlled pad drivers, and staggering the switching instants of a wide bus.