Question 3 of 6: One-Bit Full Adder in NP-Domino Logic

Question 3: One-Bit Full Adder in NP-Domino Logic (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. The same adder specification as Question 2, but the realisation must be NP-domino (NORA) logic: alternating n-type and p-type dynamic blocks clocked by a single clock, with no static inverters inserted between the dynamic stages. The reference inverter and load capacitance are unchanged.

Find. (a) an NP-domino realisation of $C_o$ and $S_o$; (b) the aspect ratio of every transistor for the same delay constraint.

Approach. Exploit the monotonicity rule that makes NP-domino work — an n-block output can only fall during evaluation and so is a legal input to a p-block, whose output can only rise. Put the carry in an n-block and the sum in the p-block that follows it, which is exactly the natural data flow of the mirror adder.

Part (a) — the circuit.

1. Recall the two block types. An n-block has a pMOS precharge device and an nMOS foot device, both gated by CLK. While $\text{CLK}=0$ the output is precharged to $V_{DD}$ and the foot is off; while $\text{CLK}=1$ the pull-down network evaluates and the output either stays high or falls. A p-block is the complement: an nMOS pre-discharge device pulls the output to ground while $\text{CLK}=0$, and during $\text{CLK}=1$ a pMOS head device lets the pull-up network evaluate, so the output either stays low or rises.
2. Understand why they must alternate. A dynamic node is monotonic during evaluation. An n-block output can only go from 1 to 0, and a falling signal only ever turns on a pMOS; conversely a p-block output can only go from 0 to 1, and a rising signal only ever turns on an nMOS. Feeding an n-block into a p-block and a p-block into an n-block therefore removes the need for the static inverter that ordinary domino logic requires, and is what NP-domino buys you.
3. Put the carry in the n-block. Re-use the pull-down network of Question 2: $A$ in series with $B$, in parallel with the pair $A\!\parallel\!B$ in series with $C_{in}$, sitting between the dynamic node and the clocked foot. During evaluation the node falls whenever the carry is 1, so the n-block output is $\overline{C_o}$, precharged high and falling — precisely the monotone signal a p-block wants.
4. Put the sum in the p-block that follows it. The pull-up network is the mirror of the sum pull-down network of Question 2: the parallel group $A\!\parallel\!B\!\parallel\!C_{in}$ in series with a device gated by $\overline{C_o}$, in parallel with $A$, $B$ and $C_{in}$ in series, all fed from the clocked head device. Checking the eight input patterns shows this network conducts exactly when $S_o=0$, so the pre-discharged node rises to give $\overline{S_o}$. Two small output inverters then produce the true $C_o$ and $S_o$ and drive the specified load: $$\boxed{7\ \text{(n-block)}+9\ \text{(p-block)}+4\ \text{(two output inverters)}=20\ \text{transistors,}}$$ eight fewer than the static design, and with only nMOS devices in the carry evaluation path.
5. Check the timing discipline. Both blocks evaluate in the same clock phase, so the carry must settle before the sum block's own evaluation completes. The inputs $A$, $B$ and $C_{in}$ must be stable before the rising clock edge; $\overline{C_o}$ is the only signal that moves during evaluation, and it moves in the falling direction that the p-block tolerates.

Part (b) — the sizing. The rule is the same equivalent-resistance argument as Question 2, with one addition: the clocked foot and head transistors are in the conduction path and must be counted in the series depth.

1. Count the n-block evaluation path. The deepest path is two evaluation nMOS devices plus the clocked foot, i.e. three in series, so every nMOS in the n-block — evaluation devices and foot alike — is sized $3(W/L)_n$.
2. Size the n-block precharge device. It is the only device in the pull-up path, so $(W/L)_p$ is sufficient to restore the node in one precharge phase. Making it larger only loads the clock.
3. Count the p-block evaluation path. The deepest path is the three series pMOS devices plus the clocked head, four in series, so those four take $4(W/L)_p$. The branch through the parallel group and the $\overline{C_o}$ device is only three deep including the head, so those devices take $3(W/L)_p$.
4. Size the p-block pre-discharge device at $(W/L)_n$, again because it is alone in its path.
5. Size the two output inverters at the reference $(W/L)_n$ and $(W/L)_p$, since each drives exactly the load capacitance named in the question: $$\boxed{(W/L)_{n,\text{inv}}=(W/L)_n,\qquad (W/L)_{p,\text{inv}}=(W/L)_p.}$$