Dynamic Power Dissipation of a Laid-Out Inverter: 22-Elec-B6 Integrated Circuit Engineering, May 2017, Q6

Question 6: Dynamic Power Dissipation of a Laid-Out Inverter (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given.

Quantity	Symbol	Value
Gate length (polysilicon width)	$L$	0.35 µm
pMOS channel width (active height)	$W_p$	1.75 µm
nMOS channel width (active height)	$W_n$	0.70 µm
Source/drain diffusion length either side of the gate	$L_{diff}$	0.85 µm
Gate capacitance per unit area	$C_{ox}$	3.5 fF/µm$^2$
p-substrate doping / n-well doping	$N_{A,sub}$, $N_{D,nwell}$	$10^{16}\ \text{cm}^{-3}$
Source/drain doping (both types)	$N_D$, $N_A$	$10^{19}\ \text{cm}^{-3}$
Electron charge	$q$	$1.6\times10^{-19}$ C
Silicon permittivity	$\epsilon_s$	$1.05\times10^{-12}$ F/cm
Intrinsic carrier concentration	$n_i$	$1.5\times10^{10}\ \text{cm}^{-3}$
Thermal voltage	$\phi_t$	26 mV
Supply / voltage swing	$V_{DD}$	1.2 V
Input square-wave frequency	$f$	1 GHz

Find. The dynamic power dissipated by the inverter when its input and output both swing over the full 0–1.2 V range at 1 GHz, counting every capacitance that the layout actually charges and discharges.

Figure 6.1 — the geometry extracted from Fig.Q6. The gate area of each device is $W\times L$; the shaded drain islands are the two junctions whose reverse bias swings with the output. The source islands sit on the rails and never swing.

Check: the layout of Fig.Q6 carries two families of dimensions. The inner active islands are 0.85 µm long either side of the 0.35 µm gate and 1.75 µm (pMOS) and 0.70 µm (nMOS) high; the outer 1.0 µm, 1.2 µm and 2.5 µm dimensions are the enclosing n-well and metal strap boundaries. Only the active islands enter this calculation, and the 2.5 : 1 ratio of the two channel widths is the usual mobility-matched inverter ratio, which confirms the reading.

Approach. Dynamic power is $P=C_{tot}V_{DD}^2f$, so the whole question is an inventory of capacitance. Two nodes swing: the input, whose capacitance is the two gate oxide capacitances, and the output, whose capacitance is the two drain junctions evaluated as large-signal equivalents over a 0 to $V_{DD}$ reverse-bias swing.

Compute the built-in potential of the junctions. Both drain junctions are $10^{19}$ into $10^{16}$, so both have the same built-in potential: $$\phi_o=\phi_t\ln\!\left(\frac{N_AN_D}{n_i^2}\right) =0.026\ln\!\left(\frac{10^{16}\times10^{19}}{(1.5\times10^{10})^2}\right) =0.026\times33.73=0.8769\ \text{V}.$$
Compute the zero-bias junction capacitance per unit area. Substituting into the formula supplied with the paper, $$\begin{aligned} C_{Jo}&=\sqrt{\frac{q\epsilon_s}{2}\cdot\frac{N_AN_B}{N_A+N_B}\cdot\frac{1}{\phi_o}}\\ &=\sqrt{\frac{(1.6\times10^{-19})(1.05\times10^{-12})}{2}\cdot \frac{9.99\times10^{15}}{0.8769}}\\ &=3.094\times10^{-8}\ \text{F/cm}^2. \end{aligned}$$ Converting to layout units, $1\ \text{cm}^2=10^{8}\ \mu\text{m}^2$, so $C_{Jo}=0.3094$ fF/µm$^2$.
Average the junction capacitance over the voltage swing. The junction capacitance is bias dependent, so the paper supplies the large-signal (charge-equivalent) form. With the reverse bias swinging between $V_{R1}=0$ and $V_{R2}=1.2$ V, $$\begin{aligned} K_{eq}&=\left|\frac{2\sqrt{\phi_o}}{V_{R1}-V_{R2}} \left(\sqrt{V_{R2}+\phi_o}-\sqrt{V_{R1}+\phi_o}\right)\right|\\ &=\frac{2\sqrt{0.8769}}{1.2}\left(\sqrt{2.0769}-\sqrt{0.8769}\right)=0.7877, \end{aligned}$$ so the equivalent capacitance per unit area over the transition is $$C_J=K_{eq}C_{Jo}=0.7877\times0.3094=0.2437\ \text{fF}/\mu\text{m}^2.$$ The same figure serves both devices: the nMOS drain is n$^+$ in the p-substrate and the pMOS drain is p$^+$ in the n-well, and both junctions see a reverse bias that sweeps between 0 and $V_{DD}$ as the output swings.
Total the gate capacitance at the input node. Neglecting overlap and fringe contributions as instructed, the gate capacitance of each device is $C_{ox}WL$: $$A_{G,n}=0.70\times0.35=0.2450\ \mu\text{m}^2,\qquad A_{G,p}=1.75\times0.35=0.6125\ \mu\text{m}^2,$$ $$C_{gate}=3.5\times(0.2450+0.6125)=3.001\ \text{fF}.$$
Total the junction capacitance at the output node. With sidewall capacitance neglected, only the bottom-plate area of each drain island counts: $$A_{D,n}=0.70\times0.85=0.5950\ \mu\text{m}^2,\qquad A_{D,p}=1.75\times0.85=1.4875\ \mu\text{m}^2,$$ $$C_{db}=0.2437\times(0.5950+1.4875)=0.5074\ \text{fF}.$$ The two source islands are deliberately excluded: the nMOS source sits on ground and the pMOS source on $V_{DD}$, so neither junction's reverse bias ever changes and neither stores or releases charge.
Add the two and evaluate the power. $$C_{tot}=C_{gate}+C_{db}=3.001+0.507=3.509\ \text{fF},$$ and with one complete charge-and-discharge cycle per input period, $$P_{dyn}=C_{tot}V_{DD}^2f=3.509\times10^{-15}\times(1.2)^2\times10^{9},$$ $$\boxed{P_{dyn}=5.05\ \mu\text{W}.}$$
Sanity-check the split. The input gate capacitance accounts for $4.32\ \mu$W and the output junctions for $0.73\ \mu$W, so 86 per cent of the dissipation is the gate oxide. That is the expected result for a minimum-size inverter in a 0.35 µm process and is why fan-out, not drain area, dominates the power budget of a logic path.

Quantity	Value
Built-in potential $\phi_o$	0.8769 V
Zero-bias junction capacitance $C_{Jo}$	$3.094\times10^{-8}$ F/cm$^2$ = 0.3094 fF/µm$^2$
Large-signal factor $K_{eq}$ (0 to 1.2 V)	0.7877
Equivalent junction capacitance $C_J$	0.2437 fF/µm$^2$
Gate areas (nMOS, pMOS)	0.2450 and 0.6125 µm$^2$
Drain areas (nMOS, pMOS)	0.5950 and 1.4875 µm$^2$
Input gate capacitance $C_{gate}$	3.001 fF
Output junction capacitance $C_{db}$	0.507 fF
Total switched capacitance $C_{tot}$	3.509 fF
Dynamic power at 1 GHz, 1.2 V	5.05 µW (4.32 µW input, 0.73 µW output)

Topic. Extracting capacitance from a layout and computing switching power.

Key relations. $P_{dyn}=C_{tot}V_{DD}^2f$; $C_{gate}=C_{ox}WL$; $\phi_o=\phi_t\ln(N_AN_D/n_i^2)$; $C_{Jo}=\sqrt{(q\epsilon_s/2)(N_AN_B/(N_A+N_B))/\phi_o}$; the large-signal factor $K_{eq}$ that converts the bias-dependent junction capacitance into a single equivalent value for a given voltage swing.

Why this works. Every cycle, a charge $C_{tot}V_{DD}$ is taken from the supply and returned to ground, and the energy $C_{tot}V_{DD}^2$ per cycle is dissipated in the channel resistances regardless of how fast or slow the transition is — which is why the answer needs no information about device strength. The only genuine subtlety is the junction capacitance: it varies as $(1+V_R/\phi_o)^{-1/2}$, so no single value is correct at every instant. The supplied formula performs the correct averaging, equating the charge actually moved over the swing to an equivalent linear capacitor, which is the only average that gives the right energy.

Common pitfall. Including the source junctions (their bias never changes, so they carry no dynamic power); using $C_{Jo}$ directly instead of the large-signal $K_{eq}C_{Jo}$, which overstates the junction contribution by about 27 per cent; and unit slips in the F/cm$^2$ to fF/µm$^2$ conversion, which is a factor of $10^{8}$ in area and $10^{15}$ in capacitance.

Source. Rabaey, Chandrakasan and Nikolic, Digital Integrated Circuits, 2nd ed., Chapter 3 (The Devices — junction and MOS capacitance, the $K_{eq}$ derivation) and Chapter 5 (The CMOS Inverter — power); Weste and Harris, CMOS VLSI Design, 4th ed., Chapter 8 (Circuit simulation and parasitics).

Question 6 of 6: Dynamic Power Dissipation of a Laid-Out Inverter

Question 6: Dynamic Power Dissipation of a Laid-Out Inverter (20 marks)