Question 2 of 6: One-Bit Full Adder in Complementary Static CMOS

Question 2: One-Bit Full Adder in Complementary Static CMOS (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Inputs $A$, $B$, $C_{in}$; outputs $S_o$ and $C_o$; a reference static CMOS inverter of aspect ratios $(W/L)_n$ and $(W/L)_p$ whose load capacitance is also the load on $S_o$ and on $C_o$. The adder must be built from complementary static CMOS gates only.

Find. (1) a complementary static CMOS realisation of $C_o$ and of $S_o$; (2) the aspect ratio of every transistor such that each stage delivers the same $t_{pHL}$ and $t_{pLH}$ as the reference inverter.

Approach. Factor the two adder functions so that the carry is generated once and reused by the sum, build each as an inverting complementary gate followed by an output inverter, then size every device by the number of like-type transistors in series in its worst-case conduction path.

Part (1) — the logic.

1. Factor the carry so that only two transistors ever sit in series. The carry-out of a full adder is the majority function, which factors as $$C_o=AB+BC_{in}+AC_{in}=AB+(A+B)\,C_{in}.$$ A complementary CMOS gate is naturally inverting, so the pull-down network implements the conduction condition $AB+(A+B)C_{in}$ and the gate output is $\overline{C_o}$. The deepest series path is two nMOS transistors, which is the whole point of this factoring: the ripple path through a carry chain is the critical path of a multi-bit adder.
2. Use the mirror topology for the pull-up network. The majority function is self-dual, so the pull-up network can be drawn as the same topology built from pMOS devices rather than as the formal series-parallel dual. Checking all eight input patterns confirms the pull-up conducts exactly when $C_o=0$. That symmetry is what gives the structure its name — the mirror adder — and it makes the layout regular and the rise and fall paths equally deep.
3. Express the sum in terms of the carry already generated. A three-input exclusive-OR would need long series stacks, so use the standard identity $$S_o=(A+B+C_{in})\,\overline{C_o}+A\,B\,C_{in},$$ which reproduces $A\oplus B\oplus C_{in}$ for all eight input patterns. Only the majority term is expensive, and it has already been computed.
4. Build the sum stage and buffer both outputs. The pull-down network for the sum gate is the parallel combination of $A$, $B$ and $C_{in}$ in series with a device driven by $\overline{C_o}$, in parallel with $A$, $B$ and $C_{in}$ in series; the pull-up network mirrors it. The gate therefore produces $\overline{S_o}$, and a single inverter on each of the two gate outputs delivers the true $S_o$ and $C_o$ and provides the drive for the specified load. Total device count is $$\boxed{10\ \text{(carry gate)}+14\ \text{(sum gate)}+4\ \text{(two output inverters)}=28\ \text{transistors.}}$$

Part (2) — the sizing. The delay constraint is a statement about equivalent resistance. For a step input, the propagation delay of a gate driving a capacitance $C_L$ is $t_p=0.69\,R_{eq}C_L$, so two gates driving the same load have the same delay when they have the same equivalent on-resistance.

1. State the reference resistance. The inverter's pull-down resistance is that of a single nMOS of aspect ratio $(W/L)_n$; call it $R_n$. Its pull-up resistance is that of a single pMOS of aspect ratio $(W/L)_p$, call it $R_p$. Since $R\propto L/W$, a device of aspect ratio $k\,(W/L)$ has resistance $R/k$.
2. Apply the series-stack rule. If $k$ like-type devices conduct in series and each is widened by the factor $k$, the chain resistance is $$k\times\frac{R}{k}=R,$$ i.e. exactly the reference value. So every transistor is widened by the number of like-type devices in series in the worst-case path through it. Devices in parallel are left at unit size, because in the worst case only one of them conducts.
3. Size the carry stage. Both networks are two deep, so every nMOS of the carry gate takes $2(W/L)_n$ and every pMOS takes $2(W/L)_p$.
4. Size the sum stage. The $A\,B\,C_{in}$ branch is three deep and takes $3(W/L)_n$ per nMOS (and $3(W/L)_p$ per pMOS in the mirrored branch). The parallel group $A\!\parallel\!B\!\parallel\!C_{in}$ sits in series with only the $\overline{C_o}$ device, so those four transistors need only $2(W/L)_n$ (and $2(W/L)_p$).
5. Size the output inverters. Each output inverter drives precisely the load capacitance named in the question and has a single device in each path, so it is the reference inverter itself: $$\boxed{(W/L)_{n,\text{inv}}=(W/L)_n,\qquad (W/L)_{p,\text{inv}}=(W/L)_p.}$$ This is what makes the constraint achievable at all — the transition seen at $S_o$ and at $C_o$ is produced by an inverter identical to the reference one, driving an identical load.