NivaarExam PrepOfficial exam papers ↗

23-Mechatronics-A3 Digital Logic and Embedded Systems · Undated paper

Question 2 of 6: Synchronous JK up/down counter with enable

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. This paper's cover page prints the exam code 18-Elec-A4, Digital Systems and Computers (National Examinations, May 2018), a three-hour closed-book exam with one approved calculator model permitted. The cover page states that FIVE of the SIX printed questions constitute a complete exam paper; all six are worked here, each worth 12 marks per the page-1 marking-scheme table.

Reference texts. M.M. Mano & M.D. Ciletti, Digital Design, 6th ed. (K-map minimisation and static hazards Ch.3; sequential circuit analysis/design and JK excitation Ch.5–6; PLA/PAL Ch.7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems, 6th ed. (address decoding and memory-mapped I/O Ch.1, 8); Motorola/ Freescale, M68HC11 Reference Manual (accumulator-A load/store timing, port I/O).

Questions are numbered here by matching each question's sub-part count and mark split to the marking scheme on page 1: Q1 (3+3+3+3) is the PoS/SoP K-map question on page 2; Q2 (3+3+3+3) is the JK-flip-flop counter question on page 2, whose printed bullet (c) merges two 3-mark deliverables (K-map and circuit drawing) into one line, split here into (c) and (d) to match the mark count; Q3 (6+6) is the truth-table/PLA question on page 3; Q4 (3+4+3+2) is the RS/T flip-flop question on page 3; Q5 (3+3+3+3) is the question on page 4; Q6 (4.5+4.5+3) is the question on page 5. The flip-flop excitation tables and Boolean identities on page 6 are used throughout as needed.

Question 2: Synchronous JK up/down counter with enable [3+3+3+3 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Two JK flip-flops $A,B$; inputs $E$ (enable) and $X$ (direction); $E{=}0\Rightarrow$ hold; $E{=}1,X{=}1\Rightarrow$ count up $00{\to}01{\to}10{\to}11{\to}00$; $E{=}1,X{=}0\Rightarrow$ count down $00{\to}11{\to}10{\to}01{\to}00$. JK excitation table (from the reference sheet): $Q{=}0{\to}Q^+{=}0\!:J{=}0,K{=}X$; $Q{=}0{\to}Q^+{=}1\!:J{=}1,K{=}X$; $Q{=}1{\to}Q^+{=}0\!:J{=}X,K{=}1$; $Q{=}1{\to}Q^+{=}1\!:J{=}X,K{=}0$.

Find. The state diagram, the state transition table, minimised $J_A,K_A,J_B,K_B$ as functions of $A,B,E,X$, and the resulting circuit.

Approach. Notice the down sequence is exactly the up sequence traversed backwards ($00{\to}11{\to}10{\to}01{\to}00$ reverses every edge of $00{\to}01{\to}10{\to}11{\to}00$), so both directions live on a single 4-state ring with $X$ choosing the direction of travel. From that, tabulate present/next state for all 16 combinations of $A,B,E,X$, read $J,K$ per bit off the excitation table, then K-map each of $J_A,K_A,J_B,K_B$ over $A,B,E,X$ (16-cell maps) to minimise.

00011110A B (state) — solid black: E=1,X=1 (count up, clockwise)dashed red: E=1,X=0 (count down, counter-clockwise)E=0 (either X): every state self-loops (hold) - omitted for clarity
Fig. 2(a) — state transition diagram: the same 4-state ring is traversed clockwise (count up, $X{=}1$) or counter-clockwise (count down, $X{=}0$) whenever $E{=}1$; every state self-loops when $E{=}0$ (omitted from the drawing for clarity).
  1. (b) State transition table. When $E{=}0$, every row of the excitation table reduces to $J{=}0,K{=}0$ for both flip-flops regardless of $A,B,X$ (a JK flip-flop with $J{=}K{=}0$ holds), so those 8 trivial rows are summarised in one line rather than repeated. The 8 rows with $E{=}1$:
    $AB$$X$$A^+B^+$$J_AK_A$$J_BK_B$
    000111,11,1
    001010,01,1
    010000,01,1
    011101,11,1
    100011,11,1
    101110,01,1
    110100,01,1
    111001,11,1
    When $E{=}0$: $J_A{=}K_A{=}J_B{=}K_B{=}0$ for every $A,B,X$ (hold), 8 further rows omitted as trivial.
  2. (c) K-map simplification. $J_B$ and $K_B$ are $1$ on exactly the same 8 rows ($E{=}1$, any $A,B,X$) and $0$ whenever $E{=}0$ — the K-map collapses to a single variable: $$\boxed{J_B=K_B=E}.$$ For $J_A$ ($=K_A$, by the same "always both 1 or both 0" pattern visible in the table), the K-map over $A,B,E,X$ shows $A$ never appears (both $A{=}0$ and $A{=}1$ rows give identical values for the same $B,E,X$), and the two 1-rows per $E{=}1$ block are $(B,X){=}(0,0)$ and $(B,X){=}(1,1)$ — adjacent in neither the $B$ nor $X$ direction, so no further grouping is possible beyond the two minterms $E\bar B\bar X$ and $EBX$: $$\boxed{J_A=K_A=EB X+E\bar B\bar X=E(B\odot X)}$$ (using $B\odot X$ for the XNOR of $B$ and $X$, i.e. $A$ toggles when enabled and $B$ agrees with the direction bit).
  3. (d) Resulting circuit. One XNOR gate combines $B$ and $X$; its output ANDed with $E$ drives $J_A$ and $K_A$ (tied together); $E$ drives $J_B$ and $K_B$ directly (also tied together). Both flip-flops share the same clock edge.
    XNORBXANDE(also drives JB=KB directly)JA = KA= E.(B XNOR X)FF A (JK)FF B (JK)JB = KB = EClk (common, not shown) drives both FFs on the active edge
    Fig. 2(d) — combinational logic: XNOR(B,X) AND E feeds $J_A{=}K_A$; E feeds $J_B{=}K_B$ directly.
QuantityResult
$J_A=K_A$$E(B\odot X)=EBX+E\bar B\bar X$
$J_B=K_B$$E$
Topology4-state ring, direction set by $X$, held by $E{=}0$
Check. Every row of the state table and both boxed equations are re-derived from the JK characteristic equation $Q^+=J\bar Q+\bar KQ$.