Memory-mapping a 64KB space from four 16Kx8 modules: 23-Mechatronics-A3 Digital Logic and Embedded Systems, Undated paper, Q6

Question 6: Memory-mapping a 64KB space from four 16Kx8 modules [4.5+4.5+3 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. An 8-bit CPU with a 16-line address bus $A_{15}\ldots A_0$ (so $2^{16}=65536=64\text{K}$ bytes of address space) and an 8-line data bus $D_7\ldots D_0$; memory modules of size $16\text{K}\times 8$ (each needs $\log_2(16\times1024)=14$ address lines and all 8 data lines).

Find. How many modules are needed and how their address/data pins connect to the bus; the chip-select logic; the address range of each module.

Approach. $64\text{K}/16\text{K}=4$ modules exactly fill the space. Since each module only needs 14 of the 16 address lines, connect $A_{13}\ldots A_0$ identically to every module (they select the byte WITHIN a module) and use the 2 remaining high-order lines $A_{15},A_{14}$ to generate 4 mutually-exclusive chip-select signals, one per module — a textbook 2-to-4 decode built from AND gates on $A_{15},A_{14}$ and their complements.

Fig. 6 — 4× 16Kx8 modules sharing $A_{13}$–$A_0$ (14 lines) and $D_7$–$D_0$ (8 lines); $A_{15},A_{14}$ decoded into the 4 chip-selects.

(a) Module count and bus connections. $64\times1024/(16\times1024)=4$ modules. Each module's address pins connect to $A_{13}\ldots A_0$ (14 lines, the "blank box" above each module's address bus = 14) and its data pins connect to all of $D_7\ldots D_0$ (8 lines, shared by every module since only the selected one drives the bus). $$\boxed{4\text{ modules},\ 14\text{ address lines per module},\ 8\text{ shared data lines}}.$$
(b) Chip-select logic. The 2 leftover address lines $A_{15},A_{14}$ give $2^2=4$ combinations, one per module, via 2-input AND gates: $$\boxed{CS_0=\bar A_{15}\bar A_{14},\quad CS_1=\bar A_{15}A_{14},\quad CS_2=A_{15}\bar A_{14},\quad CS_3=A_{15}A_{14}}.$$ Exactly one $CS_i$ is asserted for any address, since the 4 AND-gate outputs are a minterm decode of $A_{15}A_{14}$ and minterms are mutually exclusive by construction.
(c) Address ranges. Each module occupies a contiguous $16\text{K}=0x4000$-byte block, ordered by the value of $A_{15}A_{14}$ (the block that module's 14 shared low address lines then span in full):
Module $A_{15}A_{14}$ Address range

0 00 0x0000–0x3FFF

1 01 0x4000–0x7FFF

2 10 0x8000–0xBFFF

3 11 0xC000–0xFFFF

Module	$A_{15}A_{14}$	Address range
0	00	0x0000–0x3FFF
1	01	0x4000–0x7FFF
2	10	0x8000–0xBFFF
3	11	0xC000–0xFFFF

Quantity	Result
Modules needed	4 × 16Kx8
Per-module address lines	$A_{13}$–$A_0$ (14, shared)
Chip-select equations	$CS_i$ from a 2-input AND decode of $A_{15},A_{14}$ (4 combinations)
Address ranges	0x0000–0x3FFF, 0x4000–0x7FFF, 0x8000–0xBFFF, 0xC000–0xFFFF

Concept & Theory

Topic. Linear (full) address decoding to map several memory modules into a flat address space.

Key relations. A module of size $2^n$ needs exactly $n$ address lines connected directly to it; the remaining $(\text{total lines}-n)$ high-order lines are decoded (fully, with no address foldback) into one chip-select per module, using a minterm/AND-gate decode or an off-the-shelf 2-to-4/3-to-8 decoder.

Why this works. Because $4\times16\text{K}=64\text{K}$ exactly, no address bits are wasted and no foldback/aliasing occurs (contrast Question 5, where only 3 of 16 address lines were decoded on purpose, aliasing across the whole space) — every one of the 4 chip-select minterms corresponds to exactly one contiguous, non-overlapping 16K block, and the AND-gate decode is inherently mutually exclusive so no two modules can ever be selected at once.

Common pitfall. Wiring $A_{15}$ or $A_{14}$ into the module's own 14 address lines by mistake (double-using an address bit) — the module gets exactly the number of address lines that matches its own size, and every remaining line goes to decode, never both.

Source. Hamacher, Vranesic, Zaky & Manjikian, Computer Organization and Embedded Systems §8 (memory system organisation, address decoding).

Question 6 of 6: Memory-mapping a 64KB space from four 16Kx8 modules

Question 6: Memory-mapping a 64KB space from four 16Kx8 modules [4.5+4.5+3 = 12]