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23-Mechatronics-A3 Digital Logic and Embedded Systems · Undated paper

Question 4 of 6: RS/T flip-flop circuit — analysis and machine classification

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. This paper's cover page prints the exam code 18-Elec-A4, Digital Systems and Computers (National Examinations, May 2018), a three-hour closed-book exam with one approved calculator model permitted. The cover page states that FIVE of the SIX printed questions constitute a complete exam paper; all six are worked here, each worth 12 marks per the page-1 marking-scheme table.

Reference texts. M.M. Mano & M.D. Ciletti, Digital Design, 6th ed. (K-map minimisation and static hazards Ch.3; sequential circuit analysis/design and JK excitation Ch.5–6; PLA/PAL Ch.7); C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian, Computer Organization and Embedded Systems, 6th ed. (address decoding and memory-mapped I/O Ch.1, 8); Motorola/ Freescale, M68HC11 Reference Manual (accumulator-A load/store timing, port I/O).

Questions are numbered here by matching each question's sub-part count and mark split to the marking scheme on page 1: Q1 (3+3+3+3) is the PoS/SoP K-map question on page 2; Q2 (3+3+3+3) is the JK-flip-flop counter question on page 2, whose printed bullet (c) merges two 3-mark deliverables (K-map and circuit drawing) into one line, split here into (c) and (d) to match the mark count; Q3 (6+6) is the truth-table/PLA question on page 3; Q4 (3+4+3+2) is the RS/T flip-flop question on page 3; Q5 (3+3+3+3) is the question on page 4; Q6 (4.5+4.5+3) is the question on page 5. The flip-flop excitation tables and Boolean identities on page 6 are used throughout as needed.

Question 4: RS/T flip-flop circuit — analysis and machine classification [3+4+3+2 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. RS flip-flop with state $A$ (output $A$, i.e. $Q_A$) and T flip-flop with state $B$ (output $B$, i.e. $Q_B$), both clocked on the same edge. From the figure: $S_A$ (RS flip-flop's Set input) is the AND of $X$ and $B$; $R_A$ (Reset input) is the OR of $X$ and $B$; $T_B$ (T flip-flop's toggle input) is driven directly by $A$; the circuit output $Y$ is the AND of $A$ and $\bar B$ (the T flip-flop's inverted output). RS characteristic behaviour: $S{=}1,R{=}0\Rightarrow Q^+{=}1$; $S{=}0,R{=}1\Rightarrow Q^+{=}0$; $S{=}0,R{=}0\Rightarrow Q^+{=}Q$ (hold); $S{=}1,R{=}1$ is the forbidden input combination. T flip-flop: $Q^+=T\oplus Q$.

Find. $R_A,S_A,T_B,Y$ as logic expressions; the full state transition table; the state diagram; whether the machine is Moore or Mealy.

Approach. Read the four expressions directly off the given circuit, then evaluate all 8 combinations of $A,B,X$: apply the RS rule to get $A^*$ (flagging the forbidden $S_A{=}R_A{=}1$ case explicitly rather than guessing a resolution) and the T rule to get $B^*$, then classify Moore/Mealy by checking whether $Y$ ever depends on $X$.

  1. (a) Logic expressions. $$\boxed{S_A=XB,\quad R_A=X+B,\quad T_B=A,\quad Y=A\bar B}.$$
  2. (b) State transition table. Applying $S_A,R_A,T_B,Y$ and then the RS/T update rules to all 8 combinations of $A,B,X$:
    ABX$R_A$$S_A$$T_B$$A^*$$B^*$Y
    000000000
    001100000
    010100010
    011110forbidden10
    100001111
    101101011
    110101000
    111111forbidden00
    Whenever $X{=}1$ and $B{=}1$ simultaneously, $S_A{=}XB{=}1$ and $R_A{=}X{+}B{=}1$ at the same time — the forbidden RS input. This is a genuine race/design flaw in the given circuit (not an authoring assumption): the two rows $(A,B,X){=}(0,1,1)$ and $(1,1,1)$ leave $A^*$ undefined by the RS flip-flop's own specification. $B^*$ and $Y$ remain well-defined in every row since they come from $T_B{=}A$ and $Y{=}A\bar B$, neither of which touches the forbidden condition.
  3. (c) State transition diagram. Plotting only the well-defined transitions (the two forbidden rows are shown as dashed stubs rather than resolved arrows):
    X=0,1X=0X=1: S=R=1forbiddenX=0X=1X=0X=1: forbiddenAB=00AB=01AB=10AB=11
    Fig. 4(c) — state transition diagram for $AB$; solid arrows are well-defined RS/T transitions, dashed red stubs mark the $S_A{=}R_A{=}1$ forbidden condition at $AB{=}01,X{=}1$ and $AB{=}11,X{=}1$.
  4. (d) Moore or Mealy? $Y=A\bar B$ depends only on the present state $(A,B)$ — it never appears as a function of $X$ in the table above (rows $(1,0,0)$ and $(1,0,1)$ both give $Y{=}1$; rows $(1,1,0)$ and $(1,1,1)$ both give $Y{=}0$; and so on for every state, regardless of $X$). $$\boxed{\text{This is a Moore machine}}\text{: the output is a function of state alone.}$$
QuantityResult
$S_A$$XB$
$R_A$$X+B$
$T_B$$A$
$Y$$A\bar B$
Forbidden condition$X{=}1$ and $B{=}1$ together (rows $AB{=}01,11$ at $X{=}1$)
Machine typeMoore ($Y$ depends only on present state)
Check. Every row of the state table, including the two forbidden-input rows, and the Moore-machine conclusion.