HC11 address decoding and I/O port routing: 23-Mechatronics-A3 Digital Logic and Embedded Systems, Undated paper, Q5

Question 5: HC11 address decoding and I/O port routing [3+3+3+3 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A 3:8 decoder whose 3 address inputs are wired to HC11 address lines $A_2$ (MSB), $A_1$, $A_0$ (LSB) — i.e. it decodes ONLY the low 3 bits of the 16-bit address bus, nothing higher. Its active-low output $Y_0$ (asserted when those 3 bits $=000$) clocks a D flip-flop whose D input is HC11 data-bus line D0; $Y_0$ pulses low during the STA bus cycle and returns high at the end of the cycle, which is the active clock edge. The flip-flop's $Q$ output closes the switch to the HOST I/O port; $\bar Q$ closes the switch to the MCU I/O port. Outputs $Y_1$–$Y_7$ are not wired to anything in this circuit.

Find. For each option: does the store address's low 3 bits select $Y_0$ (does the flip-flop clock at all), and if so, what does the stored byte's bit D0 route PD0 to?

Approach. Because the decoder inputs are literally address-bus bits $A_2A_1A_0$ and nothing else, the flip-flop clocks on EVERY store whose target address is a multiple of 8, regardless of the address's higher bits — so the first check per option is address mod 8, not which "block" the address looks like it belongs to. When it does clock, the captured value is bit 0 of the byte just loaded into accumulator A.

Fig. 5 — A2A1A0 decode a 3:8 decoder; $Y_0$ clocks a D flip-flop loaded from data-bus D0; Q/Qbar close the HOST/MCU routing switches.

Address low-3-bits check. All four target addresses end in a hex 0 (0x8000, 0x4000, 0x5000, 0x2500), so all four have their low 3 address bits equal to $000$ — every option selects $Y_0$ and clocks the flip-flop. This is the deliberate trap in the question: the four addresses look like they land in different "regions," but the decoder only ever looks at $A_2A_1A_0$, so the region is irrelevant — none of the four is "No Action."
(a) $xx=0x10=00010000_2$, bit D0 $=0$. $Q{=}0\Rightarrow\bar Q{=}1\Rightarrow$ switch to MCU closes. $$\boxed{\text{(a) MCU I/O port}}.$$
(b) $xx=0x29=00101001_2$, bit D0 $=1$. $Q{=}1\Rightarrow$ switch to HOST closes. $$\boxed{\text{(b) HOST Comp I/O port}}.$$
(c) $xx=0xB4=10110100_2$, bit D0 $=0$. $Q{=}0\Rightarrow$ switch to MCU closes. $$\boxed{\text{(c) MCU I/O port}}.$$
(d) $xx=0xD5=11010101_2$, bit D0 $=1$. $Q{=}1\Rightarrow$ switch to HOST closes. $$\boxed{\text{(d) HOST Comp I/O port}}.$$

Option	Address low-3-bits	D0 of loaded byte	Routing
(a) 0x10 → 0x8000	000 (Y0 selected)	0	MCU I/O port
(b) 0x29 → 0x4000	000 (Y0 selected)	1	HOST Comp I/O port
(c) 0xB4 → 0x5000	000 (Y0 selected)	0	MCU I/O port
(d) 0xD5 → 0x2500	000 (Y0 selected)	1	HOST Comp I/O port

Check. Every address's low-3-bit value and every immediate byte's D0 bit, confirming all four options select $Y_0$ and reproducing the routing decisions above.

Concept & Theory

Topic. Partial (foldback) address decoding and memory-mapped output-register latching in an embedded system.

Key relations. A decoder wired to only $n$ of the $16$ address lines asserts its output for EVERY address sharing those $n$ bits, regardless of the other $16{-}n$ bits (address foldback/aliasing); a D flip-flop clocked by a pulsed chip-select is the standard technique for building a write-only latch/register from an address strobe.

Why this works. The HC11's STA instruction asserts the target address on the bus and the data on D7–D0 for the duration of the write cycle; wiring only the low-order address lines to the decoder means the circuit designer intentionally (or, here, as a teaching trap) ignores the rest of the address space, so any store whose low 3 bits are $000$ triggers the latch, "aliased" across every 8-byte-aligned page of the full 64K map.

Common pitfall. Assuming the four different-looking target addresses land in four different decode regions and therefore reading one or more as "No Action" without actually computing address mod 8 — the whole point of wiring only 3 address lines is that most of the address is a don't-care.

Source. Hamacher, Vranesic, Zaky & Manjikian, Computer Organization and Embedded Systems §1.4, §8 (address decoding, memory-mapped I/O); Motorola/Freescale, M68HC11 Reference Manual (LDAA/STAA instruction timing and the accumulator/data-bus path).

Question 5 of 6: HC11 address decoding and I/O port routing

Question 5: HC11 address decoding and I/O port routing [3+3+3+3 = 12]