K-map minimisation and PLA implementation of a multi-output circuit: 23-Mechatronics-A3 Digital Logic and Embedded Systems, Undated paper, Q3

Question 3: K-map minimisation and PLA implementation of a multi-output circuit [6+6 = 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Inputs $A,B,C$; outputs $W,X,Y,Z$:

A	B	C	W	X	Y	Z
0	0	0	0	0	0	0
0	0	1	0	0	0	1
0	1	0	0	0	1	1
0	1	1	0	1	1	1
1	0	0	1	1	1	1
1	0	1	1	1	1	0
1	1	0	1	1	0	0
1	1	1	1	0	0	0

Find. Minimal SoP for each of $W,X,Y,Z$; a PLA implementation, justified against the PAL alternative.

Approach. K-map each output separately over $A,B,C$ (Gray-code $2\times4$ maps), then compare the four minimal covers side-by-side: any product term reused by more than one output is the deciding factor between a PLA (shared, programmable OR plane) and a PAL (fixed OR plane, no sharing).

(a) K-map for $W$. Minterms $\Sigma(4,5,6,7)$ — the four cells where $A{=}1$ form a full quad regardless of $B,C$: $$\boxed{W=A}.$$
K-map for $X$. Minterms $\Sigma(3,4,5,6)$. Groups: $\{4,5\}\Rightarrow A\bar B$; $\{4,6\}\Rightarrow A\bar C$; $\{3\}$ has no adjacent 1 to pair with $\Rightarrow \bar ABC$. $$\boxed{X=A\bar B+A\bar C+\bar ABC}.$$
K-map for $Y$. Minterms $\Sigma(2,3,4,5)$. Groups: $\{2,3\}\Rightarrow \bar AB$; $\{4,5\}\Rightarrow A\bar B$ (this pair is independent of $C$ in both groups, so $Y$ does not depend on $C$ at all — $Y$ is exactly the XOR of $A$ and $B$). $$\boxed{Y=A\bar B+\bar AB}.$$
K-map for $Z$. Minterms $\Sigma(1,2,3,4)$. Groups: $\{2,3\}\Rightarrow \bar AB$; $\{1,3\}\Rightarrow \bar AC$; $\{4\}$ isolated $\Rightarrow A\bar B\bar C$. $$\boxed{Z=\bar AB+\bar AC+A\bar B\bar C}.$$
(b) PLA vs PAL. Collecting the distinct product terms used above: $\{A,\ A\bar B,\ A\bar C,\ \bar ABC,\ \bar AB,\ \bar AC,\ A\bar B\bar C\}$ — 7 distinct terms, but $A\bar B$ is reused by both $X$ and $Y$, and $\bar AB$ is reused by both $Y$ and $Z$. A PAL has a programmable AND plane but a FIXED OR plane, so each output's OR gate can only draw on its own dedicated bank of AND rows — a shared term must be physically duplicated once per output that needs it (9 total AND rows: $1+3+2+3$ for $W,X,Y,Z$ with no reuse). A PLA has a programmable OR plane as well, so a shared product line is computed once and fanned into every output that needs it (7 total AND rows). Since genuine sharing exists here ($A\bar B$, $\bar AB$), the PLA is the more area-efficient choice. $$\boxed{\text{PLA: 7 AND-plane rows} < \text{PAL: 9 AND-plane rows}}.$$

Output	Minimal SoP
$W$	$A$
$X$	$A\bar B+A\bar C+\bar ABC$
$Y$	$A\bar B+\bar AB$
$Z$	$\bar AB+\bar AC+A\bar B\bar C$
Architecture	PLA (7 AND rows, 2 shared terms) over PAL (9 rows)

Concept & Theory

Topic. Multi-output K-map minimisation and PLA/PAL architecture selection.

Key relations. K-map adjacency grouping per output; PLA = programmable AND-plane + programmable OR-plane; PAL = programmable AND-plane + FIXED OR-plane.

Why this works. Minimising each output's K-map in isolation only answers half the question — the PLA/PAL choice is a property of the OUTPUT SET as a whole, not any single output, because it hinges on whether product terms recur across outputs. Here they genuinely do ($A\bar B$, $\bar AB$), which is exactly the situation a PLA's shared, programmable OR-plane is built to exploit.

Common pitfall. Picking PLA "by default" without checking for term sharing, or minimising each K-map without ever comparing the four covers against each other — the comparison step is where the marks for part (b) actually live.

Source. Mano & Ciletti, Digital Design §3.2–3.3 (K-map minimisation) and §7.5–7.6 (PLA, PAL).

Question 3 of 6: K-map minimisation and PLA implementation of a multi-output circuit

Question 3: K-map minimisation and PLA implementation of a multi-output circuit [6+6 = 12]